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Searched refs:v32i32 (Results 1 – 25 of 89) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td88 CCIfType<[v32i32,v64i16,v128i8],
94 CCIfType<[v32i32,v64i16,v128i8],
99 CCIfType<[v32i32,v64i16,v128i8],
105 CCIfType<[v32i32,v64i16,v128i8],
120 CCIfType<[v32i32,v64i16,v128i8],
125 CCIfType<[v32i32,v64i16,v128i8],
DHexagonIntrinsics.td263 def : Pat <(v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
264 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo))>,
267 def : Pat <(v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
268 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi))>,
271 def : Pat <(v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
272 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo))>,
275 def : Pat <(v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
276 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi))>,
304 def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))),
305 (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
[all …]
DHexagonIntrinsicsV60.td15 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
16 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
18 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
19 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
21 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
22 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
24 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
25 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
46 def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))),
47 (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td118 CCIfType<[v32i32,v64i16,v128i8],
124 CCIfType<[v32i32,v64i16,v128i8],
129 CCIfType<[v32i32,v64i16,v128i8],
135 CCIfType<[v32i32,v64i16,v128i8],
150 CCIfType<[v32i32,v64i16,v128i8],
155 CCIfType<[v32i32,v64i16,v128i8],
DHexagonIntrinsicsV60.td15 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
16 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
18 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
19 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
21 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
22 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
24 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
25 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
46 def : Pat <(v128i1 (bitconvert (v32i32 HvxVR:$src1))),
47 (v128i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
DHexagonIntrinsics.td265 def : Pat <(v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
266 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo))>,
269 def : Pat <(v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
270 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi))>,
273 def : Pat <(v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
274 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo))>,
277 def : Pat <(v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
278 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi))>,
284 (v32i32 (V6_hi HvxWR:$Vdd)),
285 (v32i32 (V6_lo HvxWR:$Vdd))))>,
/external/llvm-project/llvm/test/TableGen/
Ddag-isel-subregs.td8 def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 0))),
13 def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 15))),
/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Dbitcount-128b.ll25 %t0 = call <32 x i32> @llvm.ctpop.v32i32(<32 x i32> %a0)
52 %t0 = call <32 x i32> @llvm.ctlz.v32i32(<32 x i32> %a0)
108 %t0 = call <32 x i32> @llvm.cttz.v32i32(<32 x i32> %a0)
114 declare <32 x i32> @llvm.ctpop.v32i32(<32 x i32>) #0
118 declare <32 x i32> @llvm.ctlz.v32i32(<32 x i32>) #0
122 declare <32 x i32> @llvm.cttz.v32i32(<32 x i32>) #0
Dbswap.ll35 %v0 = call <32 x i32> @llvm.bswap.v32i32(<32 x i32> %a0)
42 declare <32 x i32> @llvm.bswap.v32i32(<32 x i32>) #1
Disel-widen-truncate-pair.ll4 ; 64i8 = vpackl v32i32, for which there were no selection patterns provided.
Dwiden-ext.ll17 ; v32i8 -> v32i32
70 ; v32i16 -> v32i32
Dwiden-trunc.ll19 ; v32i32 -> v32i8
76 ; v32i32 -> v32i16
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h92 v32i32 = 43, // 32 x i32 enumerator
273 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
347 case v32i32: in getVectorElementType()
387 case v32i32: in getVectorNumElements()
506 case v32i32: in getSizeInBits()
629 if (NumElements == 32) return MVT::v32i32; in getVectorVT()
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td65 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
66 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >,
69 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
70 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >,
73 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
74 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
78 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
79 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
124 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
125 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
[all …]
DHexagonISelLowering.cpp203 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_Hexagon_VarArg()
348 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
371 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector()
419 LocVT == MVT::v32i32 || LocVT == MVT::v16i64 || in RetCC_Hexagon()
421 LocVT = MVT::v32i32; in RetCC_Hexagon()
422 ValVT = MVT::v32i32; in RetCC_Hexagon()
439 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) { in RetCC_Hexagon()
490 } else if (LocVT == MVT::v32i32) { in RetCC_HexagonVector()
545 ty == MVT::v16i64 || ty == MVT::v32i32 || ty == MVT::v64i16 || in IsHvxVectorType()
898 (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 || in getIndexedAddressParts()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h99 v32i32 = 50, // 32 x i32 enumerator
376 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
482 case v32i32: in getVectorElementType()
576 case v32i32: in getVectorNumElements()
806 case v32i32: in getSizeInBits()
965 if (NumElements == 32) return MVT::v32i32; in getVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h100 v32i32 = 51, // 32 x i32 enumerator
409 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
551 case v32i32: in getVectorElementType()
681 case v32i32: in getVectorNumElements()
945 case v32i32: in getSizeInBits()
1152 if (NumElements == 32) return MVT::v32i32; in getVectorVT()
/external/llvm/test/CodeGen/Hexagon/
Dbitconvert-vector.ll3 ; This testcase would fail on a bitcast from v64i16 to v32i32. Check that
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dbitconvert-vector.ll3 ; This testcase would fail on a bitcast from v64i16 to v32i32. Check that
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dv1024.ll3 ; Check that we do not use AGPRs for v32i32 type
/external/llvm-project/llvm/test/Analysis/CostModel/ARM/
Dreduce-umin.ll45 …ated cost of 187 for instruction: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
53 …ated cost of 237 for instruction: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
61 …ted cost of 2184 for instruction: %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
68 %V32 = call i32 @llvm.vector.reduce.umin.v32i32(<32 x i32> undef)
160 declare i32 @llvm.vector.reduce.umin.v32i32(<32 x i32>)
Dreduce-smin.ll45 …ated cost of 187 for instruction: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
53 …ated cost of 237 for instruction: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
61 …ted cost of 2184 for instruction: %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
68 %V32 = call i32 @llvm.vector.reduce.smin.v32i32(<32 x i32> undef)
160 declare i32 @llvm.vector.reduce.smin.v32i32(<32 x i32>)
Dreduce-umax.ll45 …ated cost of 187 for instruction: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
53 …ated cost of 237 for instruction: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
61 …ted cost of 2184 for instruction: %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
68 %V32 = call i32 @llvm.vector.reduce.umax.v32i32(<32 x i32> undef)
160 declare i32 @llvm.vector.reduce.umax.v32i32(<32 x i32>)
Dreduce-smax.ll45 …ated cost of 187 for instruction: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
53 …ated cost of 237 for instruction: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
61 …ted cost of 2184 for instruction: %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
68 %V32 = call i32 @llvm.vector.reduce.smax.v32i32(<32 x i32> undef)
160 declare i32 @llvm.vector.reduce.smax.v32i32(<32 x i32>)
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dreduce-mul.ll74 …imated cost of 57 for instruction: %V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
82 …imated cost of 57 for instruction: %V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
90 …imated cost of 21 for instruction: %V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
98 …imated cost of 22 for instruction: %V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
106 …imated cost of 16 for instruction: %V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
114 …imated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
121 %V32 = call i32 @llvm.vector.reduce.mul.v32i32(<32 x i32> undef)
270 declare i32 @llvm.vector.reduce.mul.v32i32(<32 x i32>)

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