Home
last modified time | relevance | path

Searched refs:Hexagon (Results 1 – 25 of 469) sorted by relevance

12345678910>>...19

/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonDepTimingClasses.h21 case Hexagon::Sched::tc_112d30d6: in is_TC1()
22 case Hexagon::Sched::tc_151bf368: in is_TC1()
23 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
24 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
25 case Hexagon::Sched::tc_23708a21: in is_TC1()
26 case Hexagon::Sched::tc_24f426ab: in is_TC1()
27 case Hexagon::Sched::tc_2f573607: in is_TC1()
28 case Hexagon::Sched::tc_388f9897: in is_TC1()
29 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
30 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
[all …]
DHexagonInstrInfo.cpp118 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), in HexagonInstrInfo()
128 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
129 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
133 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst()
134 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst()
157 if (EndLoopOp == Hexagon::ENDLOOP0) { in findLoopInstr()
158 LOOPi = Hexagon::J2_loop0i; in findLoopInstr()
159 LOOPr = Hexagon::J2_loop0r; in findLoopInstr()
161 LOOPi = Hexagon::J2_loop1i; in findLoopInstr()
162 LOOPr = Hexagon::J2_loop1r; in findLoopInstr()
[all …]
DHexagonRegisterInfo.cpp45 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/, in HexagonRegisterInfo()
50 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 || in isEHReturnCalleeSaveReg()
51 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1; in isEHReturnCalleeSaveReg()
57 using namespace Hexagon; in getCallerSavedRegs()
109 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
110 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
111 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
117 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, in getCalleeSavedRegs()
118 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
119 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
[all …]
DHexagonAsmPrinter.cpp68 assert(Hexagon::IntRegsRegClass.contains(Reg)); in getHexagonRegisterPair()
71 assert(Hexagon::DoubleRegsRegClass.contains(Pair)); in getHexagonRegisterPair()
135 if (Hexagon::DoubleRegsRegClass.contains(RegNumber)) in PrintAsmOperand()
137 Hexagon::isub_lo : in PrintAsmOperand()
138 Hexagon::isub_hi); in PrintAsmOperand()
271 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; in HexagonProcessInstruction()
277 case Hexagon::A2_iconst: { in HexagonProcessInstruction()
278 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
285 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
290 case Hexagon::A2_tfrf: { in HexagonProcessInstruction()
[all …]
DHexagonNewValueJump.cpp157 if (!Hexagon::IntRegsRegClass.contains(Op.getReg())) in INITIALIZE_PASS_DEPENDENCY()
230 if (MII->getOpcode() == Hexagon::LDriw_pred || in commonChecksToProhibitNewValueJump()
231 MII->getOpcode() == Hexagon::STriw_pred) in commonChecksToProhibitNewValueJump()
259 case Hexagon::C2_cmpeqi: in canCompareBeNewValueJump()
260 case Hexagon::C4_cmpneqi: in canCompareBeNewValueJump()
261 case Hexagon::C2_cmpgti: in canCompareBeNewValueJump()
262 case Hexagon::C4_cmpltei: in canCompareBeNewValueJump()
265 case Hexagon::C2_cmpgtui: in canCompareBeNewValueJump()
266 case Hexagon::C4_cmplteui: in canCompareBeNewValueJump()
269 case Hexagon::S2_tstbit_i: in canCompareBeNewValueJump()
[all …]
DHexagonConstExtenders.cpp799 case Hexagon::S4_storeirbt_io: in isStoreImmediate()
800 case Hexagon::S4_storeirbf_io: in isStoreImmediate()
801 case Hexagon::S4_storeirht_io: in isStoreImmediate()
802 case Hexagon::S4_storeirhf_io: in isStoreImmediate()
803 case Hexagon::S4_storeirit_io: in isStoreImmediate()
804 case Hexagon::S4_storeirif_io: in isStoreImmediate()
805 case Hexagon::S4_storeirb_io: in isStoreImmediate()
806 case Hexagon::S4_storeirh_io: in isStoreImmediate()
807 case Hexagon::S4_storeiri_io: in isStoreImmediate()
817 case Hexagon::L2_loadrub_io: in isRegOffOpcode()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepTimingClasses.h21 case Hexagon::Sched::tc_05d3a09b: in is_TC3x()
22 case Hexagon::Sched::tc_0d8f5752: in is_TC3x()
23 case Hexagon::Sched::tc_13bfbcf9: in is_TC3x()
24 case Hexagon::Sched::tc_174516e8: in is_TC3x()
25 case Hexagon::Sched::tc_1a2fd869: in is_TC3x()
26 case Hexagon::Sched::tc_1c4528a2: in is_TC3x()
27 case Hexagon::Sched::tc_32779c6f: in is_TC3x()
28 case Hexagon::Sched::tc_5b54b33f: in is_TC3x()
29 case Hexagon::Sched::tc_6b25e783: in is_TC3x()
30 case Hexagon::Sched::tc_76851da1: in is_TC3x()
[all …]
DHexagonInstrInfo.cpp118 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), in HexagonInstrInfo()
122 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
123 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
127 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst()
128 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst()
151 if (EndLoopOp == Hexagon::ENDLOOP0) { in findLoopInstr()
152 LOOPi = Hexagon::J2_loop0i; in findLoopInstr()
153 LOOPr = Hexagon::J2_loop0r; in findLoopInstr()
155 LOOPi = Hexagon::J2_loop1i; in findLoopInstr()
156 LOOPr = Hexagon::J2_loop1r; in findLoopInstr()
[all …]
DHexagonRegisterInfo.cpp45 : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/, in HexagonRegisterInfo()
50 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 || in isEHReturnCalleeSaveReg()
51 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1; in isEHReturnCalleeSaveReg()
57 using namespace Hexagon; in getCallerSavedRegs()
109 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
110 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
111 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
117 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, in getCalleeSavedRegs()
118 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
119 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
[all …]
DHexagonAsmPrinter.cpp68 assert(Hexagon::IntRegsRegClass.contains(Reg)); in getHexagonRegisterPair()
71 assert(Hexagon::DoubleRegsRegClass.contains(Pair)); in getHexagonRegisterPair()
135 if (Hexagon::DoubleRegsRegClass.contains(RegNumber)) in PrintAsmOperand()
137 Hexagon::isub_lo : in PrintAsmOperand()
138 Hexagon::isub_hi); in PrintAsmOperand()
271 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; in HexagonProcessInstruction()
277 case Hexagon::A2_iconst: { in HexagonProcessInstruction()
278 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
285 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
290 case Hexagon::A2_tfrf: { in HexagonProcessInstruction()
[all …]
DHexagonNewValueJump.cpp157 if (!Hexagon::IntRegsRegClass.contains(Op.getReg())) in INITIALIZE_PASS_DEPENDENCY()
230 if (MII->getOpcode() == Hexagon::LDriw_pred || in commonChecksToProhibitNewValueJump()
231 MII->getOpcode() == Hexagon::STriw_pred) in commonChecksToProhibitNewValueJump()
259 case Hexagon::C2_cmpeqi: in canCompareBeNewValueJump()
260 case Hexagon::C4_cmpneqi: in canCompareBeNewValueJump()
261 case Hexagon::C2_cmpgti: in canCompareBeNewValueJump()
262 case Hexagon::C4_cmpltei: in canCompareBeNewValueJump()
265 case Hexagon::C2_cmpgtui: in canCompareBeNewValueJump()
266 case Hexagon::C4_cmplteui: in canCompareBeNewValueJump()
269 case Hexagon::S2_tstbit_i: in canCompareBeNewValueJump()
[all …]
DHexagonConstExtenders.cpp800 case Hexagon::S4_storeirbt_io: in isStoreImmediate()
801 case Hexagon::S4_storeirbf_io: in isStoreImmediate()
802 case Hexagon::S4_storeirht_io: in isStoreImmediate()
803 case Hexagon::S4_storeirhf_io: in isStoreImmediate()
804 case Hexagon::S4_storeirit_io: in isStoreImmediate()
805 case Hexagon::S4_storeirif_io: in isStoreImmediate()
806 case Hexagon::S4_storeirb_io: in isStoreImmediate()
807 case Hexagon::S4_storeirh_io: in isStoreImmediate()
808 case Hexagon::S4_storeiri_io: in isStoreImmediate()
818 case Hexagon::L2_loadrub_io: in isRegOffOpcode()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.cpp104 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), in HexagonInstrInfo()
109 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
110 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
115 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) && in isDblRegForSubInst()
116 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg)); in isDblRegForSubInst()
140 if (EndLoopOp == Hexagon::ENDLOOP0) { in findLoopInstr()
141 LOOPi = Hexagon::J2_loop0i; in findLoopInstr()
142 LOOPr = Hexagon::J2_loop0r; in findLoopInstr()
144 LOOPi = Hexagon::J2_loop1i; in findLoopInstr()
145 LOOPr = Hexagon::J2_loop1r; in findLoopInstr()
[all …]
DHexagonRegisterInfo.cpp42 : HexagonGenRegisterInfo(Hexagon::R31) {} in HexagonRegisterInfo()
46 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 || in isEHReturnCalleeSaveReg()
47 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1; in isEHReturnCalleeSaveReg()
51 return Hexagon::R16 <= Reg && Reg <= Hexagon::R27; in isCalleeSaveReg()
58 using namespace Hexagon; in getCallerSavedRegs()
107 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
108 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, in getCalleeSavedRegs()
109 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 in getCalleeSavedRegs()
115 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, in getCalleeSavedRegs()
116 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, in getCalleeSavedRegs()
[all …]
DHexagonNewValueJump.cpp183 if (MII->getOpcode() == Hexagon::J2_call) in commonChecksToProhibitNewValueJump()
206 if (MII->getOpcode() == Hexagon::LDriw_pred || in commonChecksToProhibitNewValueJump()
207 MII->getOpcode() == Hexagon::STriw_pred) in commonChecksToProhibitNewValueJump()
230 if (!(isUInt<5>(v) || ((MI.getOpcode() == Hexagon::C2_cmpeqi || in canCompareBeNewValueJump()
231 MI.getOpcode() == Hexagon::C2_cmpgti) && in canCompareBeNewValueJump()
301 case Hexagon::C2_cmpeq: in getNewValueJumpOpcode()
302 return taken ? Hexagon::J4_cmpeq_t_jumpnv_t in getNewValueJumpOpcode()
303 : Hexagon::J4_cmpeq_t_jumpnv_nt; in getNewValueJumpOpcode()
305 case Hexagon::C2_cmpeqi: { in getNewValueJumpOpcode()
307 return taken ? Hexagon::J4_cmpeqi_t_jumpnv_t in getNewValueJumpOpcode()
[all …]
DHexagonAsmPrinter.cpp72 assert(Hexagon::IntRegsRegClass.contains(Reg)); in getHexagonRegisterPair()
75 assert(Hexagon::DoubleRegsRegClass.contains(Pair)); in getHexagonRegisterPair()
264 case Hexagon::A2_iconst: { in HexagonProcessInstruction()
265 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
272 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
278 case Hexagon::CONST64_Float_Real: in HexagonProcessInstruction()
279 case Hexagon::CONST64_Int_Real: in HexagonProcessInstruction()
289 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
297 case Hexagon::CONST32: in HexagonProcessInstruction()
298 case Hexagon::CONST32_Float_Real: in HexagonProcessInstruction()
[all …]
DHexagonGenPredicate.cpp114 return RC == &Hexagon::PredRegsRegClass; in INITIALIZE_PASS_DEPENDENCY()
119 using namespace Hexagon; in getPredForm()
173 case Hexagon::C2_cmpeqi: in isConvertibleToPredForm()
174 case Hexagon::C4_cmpneqi: in isConvertibleToPredForm()
190 case Hexagon::C2_tfrpr: in collectPredicateGPR()
237 if (Opc == Hexagon::C2_tfrpr || Opc == TargetOpcode::COPY) { in getPredRegFor()
247 const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass; in getPredRegFor()
267 case Hexagon::C2_cmpeq: in isScalarCmp()
268 case Hexagon::C2_cmpgt: in isScalarCmp()
269 case Hexagon::C2_cmpgtu: in isScalarCmp()
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp36 using namespace Hexagon;
173 MI.setOpcode(Hexagon::BUNDLE); in getInstruction()
203 case Hexagon::S2_allocframe: in remapInstruction()
204 if (MI.getOperand(0).getReg() == Hexagon::R29) { in remapInstruction()
205 MI.setOpcode(Hexagon::S6_allocframe_to_raw); in remapInstruction()
210 case Hexagon::L2_deallocframe: in remapInstruction()
211 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
212 MI.getOperand(1).getReg() == Hexagon::R30) { in remapInstruction()
218 case Hexagon::L4_return: in remapInstruction()
219 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
[all …]
/external/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp35 using namespace Hexagon;
283 MI.setOpcode(Hexagon::DuplexIClass0); in getSingleInstruction()
322 MI.getOpcode() == Hexagon::A4_ext) { in getSingleInstruction()
336 unsigned reg = i->getReg() - Hexagon::R0; in getSingleInstruction()
376 assert(Producer != Hexagon::NoRegister); in getSingleInstruction()
381 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) in getSingleInstruction()
382 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0; in getSingleInstruction()
387 assert(Producer != Hexagon::NoRegister); in getSingleInstruction()
420 case Hexagon::S2_storerbabs: in adjustExtendedInstructions()
421 opcode = Hexagon::S2_storerbgp; in adjustExtendedInstructions()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp36 using namespace Hexagon;
173 MI.setOpcode(Hexagon::BUNDLE); in getInstruction()
200 case Hexagon::S2_allocframe: in remapInstruction()
201 if (MI.getOperand(0).getReg() == Hexagon::R29) { in remapInstruction()
202 MI.setOpcode(Hexagon::S6_allocframe_to_raw); in remapInstruction()
207 case Hexagon::L2_deallocframe: in remapInstruction()
208 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
209 MI.getOperand(1).getReg() == Hexagon::R30) { in remapInstruction()
215 case Hexagon::L4_return: in remapInstruction()
216 if (MI.getOperand(0).getReg() == Hexagon::D15 && in remapInstruction()
[all …]
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCodeEmitter.cpp31 using namespace Hexagon;
98 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) in RegisterMatches()
99 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31) in RegisterMatches()
100 return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0); in RegisterMatches()
114 static unsigned RegMap[8] = {Hexagon::R8, Hexagon::R9, Hexagon::R10, in EncodeSingleInstruction()
115 Hexagon::R11, Hexagon::R12, Hexagon::R13, in EncodeSingleInstruction()
116 Hexagon::R14, Hexagon::R15}; in EncodeSingleInstruction()
159 : static_cast<unsigned>(Hexagon::NoRegister); in EncodeSingleInstruction()
163 : static_cast<unsigned>(Hexagon::NoRegister); in EncodeSingleInstruction()
183 MCO.setReg(Offset + Hexagon::R0); in EncodeSingleInstruction()
[all …]
DHexagonMCDuplexInfo.cpp24 using namespace Hexagon;
188 case Hexagon::L2_loadri_io: in getDuplexCandidateGroup()
195 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) { in getDuplexCandidateGroup()
205 case Hexagon::L2_loadrub_io: in getDuplexCandidateGroup()
225 case Hexagon::L2_loadrh_io: in getDuplexCandidateGroup()
226 case Hexagon::L2_loadruh_io: in getDuplexCandidateGroup()
236 case Hexagon::L2_loadrb_io: in getDuplexCandidateGroup()
246 case Hexagon::L2_loadrd_io: in getDuplexCandidateGroup()
251 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
257 case Hexagon::L4_return: in getDuplexCandidateGroup()
[all …]
DHexagonMCCompound.cpp28 using namespace Hexagon;
95 case Hexagon::C2_cmpeq: in getCompoundCandidateGroup()
96 case Hexagon::C2_cmpgt: in getCompoundCandidateGroup()
97 case Hexagon::C2_cmpgtu: in getCompoundCandidateGroup()
103 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
108 case Hexagon::C2_cmpeqi: in getCompoundCandidateGroup()
109 case Hexagon::C2_cmpgti: in getCompoundCandidateGroup()
110 case Hexagon::C2_cmpgtui: in getCompoundCandidateGroup()
116 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
122 case Hexagon::A2_tfr: in getCompoundCandidateGroup()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp31 using namespace Hexagon;
201 case Hexagon::L2_loadri_io: in getDuplexCandidateGroup()
208 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) { in getDuplexCandidateGroup()
218 case Hexagon::L2_loadrub_io: in getDuplexCandidateGroup()
238 case Hexagon::L2_loadrh_io: in getDuplexCandidateGroup()
239 case Hexagon::L2_loadruh_io: in getDuplexCandidateGroup()
249 case Hexagon::L2_loadrb_io: in getDuplexCandidateGroup()
259 case Hexagon::L2_loadrd_io: in getDuplexCandidateGroup()
264 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
270 case Hexagon::L4_return: in getDuplexCandidateGroup()
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp30 using namespace Hexagon;
200 case Hexagon::L2_loadri_io: in getDuplexCandidateGroup()
207 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) { in getDuplexCandidateGroup()
217 case Hexagon::L2_loadrub_io: in getDuplexCandidateGroup()
237 case Hexagon::L2_loadrh_io: in getDuplexCandidateGroup()
238 case Hexagon::L2_loadruh_io: in getDuplexCandidateGroup()
248 case Hexagon::L2_loadrb_io: in getDuplexCandidateGroup()
258 case Hexagon::L2_loadrd_io: in getDuplexCandidateGroup()
263 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
269 case Hexagon::L4_return: in getDuplexCandidateGroup()
[all …]

12345678910>>...19