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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dld1sw-diagnostics.s6 ld1sw z23.s, p0/z, [x13, #1, MUL VL] label
11 ld1sw z29.s, p0/z, [x3, #1, MUL VL] label
20 ld1sw z28.d, p2/z, [x28, #-9, MUL VL] label
25 ld1sw z27.d, p1/z, [x26, #8, MUL VL] label
34 ld1sw z4.d, p8/z, [x11, #1, MUL VL] label
43 ld1sw { }, p0/z, [x1, #1, MUL VL] label
48 ld1sw { z1.d, z2.d }, p0/z, [x1, #1, MUL VL] label
53 ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL] label
62 ld1sw z0.d, p0/z, [x0, x0] label
67 ld1sw z0.d, p0/z, [x0, xzr] label
[all …]
Dld1sw.s10 ld1sw z0.d, p0/z, [x0] label
16 ld1sw { z0.d }, p0/z, [x0] label
22 ld1sw { z31.d }, p7/z, [sp, #-1, mul vl] label
28 ld1sw { z21.d }, p5/z, [x10, #5, mul vl] label
34 ld1sw { z23.d }, p3/z, [sp, x8, lsl #2] label
40 ld1sw { z23.d }, p3/z, [x13, x8, lsl #2] label
46 ld1sw { z31.d }, p7/z, [sp, z31.d] label
52 ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2] label
58 ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw] label
64 ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw] label
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-intrinsics-gather-loads-64bit-scaled-offset.ll72 ; CHECK: ld1sw { z0.d }, p0/z, [x0, z0.d, lsl #2]
Dsve-masked-ldst-sext.ll31 ; CHECK: ld1sw { [[IN:z[0-9]+]].d }, [[PG:p[0-9]+]]/z, [x0]
Dsve-masked-ldst-zext.ll33 ; CHECK-NOT: ld1sw
Dsve-intrinsics-gather-loads-64bit-unscaled-offset.ll94 ; CHECK: ld1sw { z0.d }, p0/z, [x0, z0.d]
Dsve-intrinsics-gather-loads-32bit-scaled-offsets.ll216 ; CHECK: ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
227 ; CHECK: ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
Dsve-masked-gather-64b-scaled.ll81 ; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, z0.d, lsl #2]
Dsve-masked-gather-legalize.ll51 ; CHECK-DAG: ld1sw { z0.d }, p0/z, [x8, z0.d]
Dsve-split-load.ll78 ; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0]
Dsve-masked-gather-64b-unscaled.ll110 ; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, z0.d]
Dsve-intrinsics-gather-loads-32bit-unscaled-offsets.ll306 ; CHECK: ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw]
317 ; CHECK: ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw]
Dsve-intrinsics-gather-loads-vector-base-imm-offset.ll165 ; CHECK: ld1sw { z0.d }, p0/z, [z0.d, #16]
346 ; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x8, z0.d]
Dsve-masked-gather-32b-signed-scaled.ll85 ; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
Dsve-intrinsics-ld1.ll169 ; CHECK: ld1sw { z0.d }, p0/z, [x0]
Dsve-intrinsics-gather-loads-vector-base-scalar-offset.ll164 ; CHECK: ld1sw { z0.d }, p0/z, [x0, z0.d]
Dspillfill-sve.ll179 ; CHECK-DAG: ld1sw { z{{[01]}}.d }, p0/z, [sp]
180 ; CHECK-DAG: ld1sw { z{{[01]}}.d }, p0/z, [sp, #1, mul vl]
Dsve-masked-gather-32b-unsigned-scaled.ll92 ; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
Dsve-intrinsics-ld1-addressing-mode-reg-reg.ll185 ; CHECK: ld1sw { z0.d }, p0/z, [x0, x1, lsl #2]
Dsve-masked-gather-32b-signed-unscaled.ll114 ; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw]
Dsve-pred-contiguous-ldst-addressing-mode-reg-reg.ll47 ; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, x1, lsl #2]
210 ; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, x1, lsl #2]
Dsve-pred-contiguous-ldst-addressing-mode-reg-imm.ll75 ; CHECK-NEXT: ld1sw { z[[DATA:[0-9]+]].d }, p0/z, [x0, #-8, mul vl]
233 ; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0, #-1, mul vl]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc12515 "ld1rw\005ld1sb\005ld1sh\005ld1sw\004ld1w\003ld2\004ld2b\004ld2d\004ld2h"
15308 …{ 1963 /* ld1sw */, AArch64::LD1SW_D_IMM, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
15309 …{ 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1…
15310 …{ 1963 /* ld1sw */, AArch64::LD1SW_D_IMM, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__R…
15311 …{ 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg…
15312 …{ 1963 /* ld1sw */, AArch64::LD1SW_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__…
15313 …{ 1963 /* ld1sw */, AArch64::GLD1SW_D_SCALED_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg…
15314 …{ 1963 /* ld1sw */, AArch64::GLD1SW_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Re…
15315 …{ 1963 /* ld1sw */, AArch64::GLD1SW_D_SXTW_SCALED_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bA…
15316 …{ 1963 /* ld1sw */, AArch64::GLD1SW_D_SXTW_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td346 defm LD1SW_D_IMM : sve_mem_cld_si<0b0100, "ld1sw", Z_d, ZPR64>;
392 defm LD1SW_D : sve_mem_cld_ss<0b0100, "ld1sw", Z_d, ZPR64, GPR64NoXZRshifted32>;
514 …defm GLD1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1000, "ld1sw", uimm5s4, AArch64ld1s_gather_imm, …
531 …defm GLD1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1000, "ld1sw", AArch64ld1s_gather, nxv2i32>;
544 …defm GLD1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1000, "ld1sw", AArch64ld1s_gather_scaled, ZP…
561 …defm GLD1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1000, "ld1sw", AArch64ld1s_gather_sxtw, AAr…
574 …defm GLD1SW_D : sve_mem_64b_gld_sv_32_scaled<0b1000, "ld1sw", AArch64ld1s_gather_sxtw_scaled, …
/external/vixl/test/aarch64/
Dtest-assembler-sve-aarch64.cc9125 Ld1Macro ld1sw = &MacroAssembler::Ld1sw; in TEST_SVE() local
9126 ldff1_scaled_offset_helper(kSRegSize, kDRegSize, ldff1sw, ld1sw); in TEST_SVE()
9233 Ld1Macro ld1sw = &MacroAssembler::Ld1sw; in sve_ldff1_scalar_plus_vector_32_unpacked_scaled_offset() local
9234 ldff1_32_unpacked_scaled_offset_helper(kSRegSize, ldff1sw, ld1sw, UXTW); in sve_ldff1_scalar_plus_vector_32_unpacked_scaled_offset()
9235 ldff1_32_unpacked_scaled_offset_helper(kSRegSize, ldff1sw, ld1sw, SXTW); in sve_ldff1_scalar_plus_vector_32_unpacked_scaled_offset()
9283 Ld1Macro ld1sw = &MacroAssembler::Ld1sw; in sve_ldff1_scalar_plus_vector_32_unpacked_unscaled_offset() local
9284 ldff1_32_unpacked_unscaled_offset_helper(kSRegSize, ldff1sw, ld1sw, UXTW); in sve_ldff1_scalar_plus_vector_32_unpacked_unscaled_offset()
9285 ldff1_32_unpacked_unscaled_offset_helper(kSRegSize, ldff1sw, ld1sw, SXTW); in sve_ldff1_scalar_plus_vector_32_unpacked_unscaled_offset()
9318 Ld1Macro ld1sw = &MacroAssembler::Ld1sw; in sve_ldff1_scalar_plus_vector_64_scaled_offset() local
9319 ldff1_64_scaled_offset_helper(kSRegSize, ldff1sw, ld1sw); in sve_ldff1_scalar_plus_vector_64_scaled_offset()
[all …]

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