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Searched refs:VReg (Results 1 – 22 of 22) sorted by relevance

/external/llvm/lib/CodeGen/
DLiveIntervalUnion.h122 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): in Query() argument
123 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false), in Query()
138 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { in init() argument
139 assert(VReg && LIU && "Invalid arguments"); in init()
140 if (UserTag == UTag && VirtReg == VReg && in init()
147 VirtReg = VReg; in init()
165 bool isSeenInterference(LiveInterval *VReg) const;
DLiveIntervalUnion.cpp152 LiveInterval *VReg = LiveUnionI.value(); in collectInterferingVRegs() local
153 if (VReg != RecentReg && !isSeenInterference(VReg)) { in collectInterferingVRegs()
154 RecentReg = VReg; in collectInterferingVRegs()
155 InterferingVRegs.push_back(VReg); in collectInterferingVRegs()
DMachineFunction.cpp398 unsigned VReg = MRI.getLiveInVirtReg(PReg); in addLiveIn() local
399 if (VReg) { in addLiveIn()
400 assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!"); in addLiveIn()
401 return VReg; in addLiveIn()
403 VReg = MRI.createVirtualRegister(RC); in addLiveIn()
404 MRI.addLiveIn(PReg, VReg); in addLiveIn()
405 return VReg; in addLiveIn()
DLiveRangeEdit.cpp35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom() local
38 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg)); in createFrom()
40 LiveInterval &LI = LIS.getOrCreateInterval(VReg); in createFrom()
DTailDuplication.cpp222 unsigned VReg = SSAUpdateVRs[i]; in TailDuplicateAndUpdate() local
223 SSAUpdate.Initialize(VReg); in TailDuplicateAndUpdate()
227 MachineInstr *DefMI = MRI->getVRegDef(VReg); in TailDuplicateAndUpdate()
231 SSAUpdate.AddAvailableValue(DefBB, VReg); in TailDuplicateAndUpdate()
236 SSAUpdateVals.find(VReg); in TailDuplicateAndUpdate()
244 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg); in TailDuplicateAndUpdate()
DMachineRegisterInfo.cpp207 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { in getLiveInPhysReg()
209 if (I->second == VReg) in getLiveInPhysReg()
DTwoAddressInstructionPass.cpp1622 unsigned VReg = TargetRegisterInfo::index2VirtReg(i); in runOnMachineFunction() local
1623 if (MRI->use_nodbg_empty(VReg)) { in runOnMachineFunction()
1624 MachineInstr *DefMI = MRI->getVRegDef(VReg); in runOnMachineFunction()
DRegAllocFast.cpp169 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp251 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); in getVR() local
254 if (!VReg) { in getVR()
256 VReg = MRI->createVirtualRegister(RC); in getVR()
259 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
260 return VReg; in getVR()
282 unsigned VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local
283 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); in AddRegisterOperand()
299 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { in AddRegisterOperand()
302 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand()
303 VReg = NewVReg; in AddRegisterOperand()
[all …]
DInstrEmitter.h83 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
/external/llvm/lib/Target/ARM/
DThumb1RegisterInfo.cpp598 unsigned VReg = 0; in eliminateFrameIndex() local
696 VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass); in eliminateFrameIndex()
701 emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg, in eliminateFrameIndex()
704 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset); in eliminateFrameIndex()
708 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII, in eliminateFrameIndex()
711 MI.getOperand(i).ChangeToRegister(VReg, false, false, true); in eliminateFrameIndex()
DARMISelLowering.cpp2550 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); in VarArgStyleRegisters() local
2551 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in VarArgStyleRegisters()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp1831 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); in LowerFormalArguments_SVR4() local
1832 if (!VReg) in LowerFormalArguments_SVR4()
1833 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); in LowerFormalArguments_SVR4()
1835 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); in LowerFormalArguments_SVR4()
1850 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); in LowerFormalArguments_SVR4() local
1851 if (!VReg) in LowerFormalArguments_SVR4()
1852 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); in LowerFormalArguments_SVR4()
1854 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); in LowerFormalArguments_SVR4()
2016 unsigned VReg; in LowerFormalArguments_Darwin() local
2018 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_Darwin()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp841 unsigned VReg = in LowerFormalArguments() local
843 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
844 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
846 unsigned VReg = in LowerFormalArguments() local
848 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
849 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp211 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments() local
212 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
213 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in LowerFormalArguments()
323 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments() local
324 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); in LowerFormalArguments()
325 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); in LowerFormalArguments()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1124 unsigned VReg = RegInfo.createVirtualRegister( in LowerCCCArguments() local
1126 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1127 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerCCCArguments()
1175 unsigned VReg = RegInfo.createVirtualRegister( in LowerCCCArguments() local
1177 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
1178 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in LowerCCCArguments()
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp636 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); in LowerLOAD() local
647 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); in LowerLOAD()
648 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); in LowerLOAD()
831 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); in LowerSTORE() local
842 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag); in LowerSTORE()
843 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT); in LowerSTORE()
1185 unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass); in LowerFormalArguments() local
1186 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
1187 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT); in LowerFormalArguments()
1233 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::VECREGRegClass); in LowerFormalArguments() local
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h425 unsigned getLiveInPhysReg(unsigned VReg) const;
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp333 unsigned VReg = in LowerCCCArguments() local
335 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
336 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp766 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); in AddLiveIn() local
767 MF.getRegInfo().addLiveIn(PReg, VReg); in AddLiveIn()
768 return VReg; in AddLiveIn()
2706 unsigned VReg = AddLiveIn(MF, *Reg, Mips::CPU64RegsRegisterClass); in CopyMips64ByValRegs() local
2709 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64), in CopyMips64ByValRegs()
/external/webkit/Source/JavaScriptCore/jit/
DJIT.h536 void emitJumpSlowCaseIfNotJSCell(RegisterID, int VReg);
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp2007 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], in LowerFormalArguments() local
2009 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments()
2034 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], in LowerFormalArguments() local
2036 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); in LowerFormalArguments()