/external/llvm/lib/Target/ |
D | TargetInstrInfo.cpp | 30 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass() function in TargetInstrInfo 44 return TRI->getRegClass(RegClass); in getRegClass()
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D | TargetRegisterInfo.cpp | 116 return getRegClass(Base + CountTrailingZeros_32(Common)); in getCommonSubClass()
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/external/llvm/lib/CodeGen/ |
D | VirtRegMap.cpp | 93 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); in assignVirt2StackSlot() 221 << MRI.getRegClass(Reg)->getName() << "\n"; in print() 229 << "] " << MRI.getRegClass(Reg)->getName() << "\n"; in print()
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D | RegisterCoalescer.cpp | 266 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src)); in setRegisters() 269 } else if (!MRI.getRegClass(Src)->contains(Dst)) { in setRegisters() 282 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters() 283 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters() 299 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters() 300 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters() 686 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg))) in RemoveCopyByCommutingDef() 795 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI); in ReMaterializeTrivialDef() 797 if (MRI->getRegClass(DstReg) != RC) in ReMaterializeTrivialDef() 1043 const TargetRegisterClass *RC = MRI->getRegClass(CP.getSrcReg()); in shouldJoinPhys() [all …]
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D | PeepholeOptimizer.cpp | 232 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY() 320 if (MRI->getRegClass(SrcSrc) != MRI->getRegClass(Def)) in OptimizeBitcastInstr()
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D | AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); in AllocationOrder()
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D | MachineRegisterInfo.cpp | 53 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass() 68 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
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D | MachineSink.cpp | 126 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY() 127 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() 498 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg))) in FindSuccToSinkTo()
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D | RegAllocBase.cpp | 188 << MRI->getRegClass(VirtReg->reg)->getName() in allocatePhysRegs() 209 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); in allocatePhysRegs()
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D | LiveRangeEdit.cpp | 35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom() 321 << MRI.getRegClass(LI.reg)->getName() << '\n'); in calculateRegClassAndHint()
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D | OptimizePHIs.cpp | 168 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) in OptimizeBB()
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D | CalcSpillWeights.cpp | 79 const TargetRegisterClass *rc = mri.getRegClass(reg); in copyHint()
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D | InlineSpiller.cpp | 728 MRI.getRegClass(SVI.SpillReg), &TRI); in hoistSpill() 1083 MRI.getRegClass(NewLI.reg), &TRI); in insertReload() 1097 MRI.getRegClass(NewLI.reg), &TRI); in insertSpill() 1226 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original)); in spillAll() 1277 << MRI.getRegClass(edit.getReg())->getName() in spill()
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D | Spiller.cpp | 88 const TargetRegisterClass *trc = mri->getRegClass(li->reg); in trivialSpillEverywhere()
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D | TwoAddressInstructionPass.cpp | 1301 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI); in TryInstructionTransform() 1522 const TargetRegisterClass *rc = MRI->getRegClass(regB); in runOnMachineFunction() 1724 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices, in CoalesceExtSubRegs() 1731 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices, in CoalesceExtSubRegs() 1861 !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg), in EliminateRegSequences() 1862 MRI->getRegClass(SrcReg), SubIdx)) { in EliminateRegSequences()
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D | UnreachableBlockElim.cpp | 201 MRI.constrainRegClass(Input, MRI.getRegClass(Output)); in runOnMachineFunction()
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D | TargetInstrInfoImpl.cpp | 278 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); in canFoldCopy() 283 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) in canFoldCopy()
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D | MachineLICM.cpp | 782 const TargetRegisterClass *RC = MRI->getRegClass(Reg); in getRegisterClassIDAndCost() 1263 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI); in ExtractHoistableLoad() 1358 OrigRCs.push_back(MRI->getRegClass(DupReg)); in EliminateCSE() 1360 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) { in EliminateCSE()
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D | MachineCSE.cpp | 142 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg))) in INITIALIZE_PASS_DEPENDENCY() 489 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg); in ProcessBlock()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | InstrEmitter.cpp | 118 RC = TII->getRegClass(II, i+II.getNumDefs(), TRI); in EmitCopyFromReg() 142 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg() 199 const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI); in CreateVirtualRegisters() 217 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); in CreateVirtualRegisters() 296 DstRC = TII->getRegClass(*II, IIOpNum, TRI); in AddRegisterOperand() 404 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg() 511 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) in EmitSubregNode() 551 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx); in EmitCopyToRegClassNode() 568 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); in EmitRegSequence() 585 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence()
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/external/llvm/lib/Target/PTX/ |
D | PTXMFInfoExtract.cpp | 60 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); in runOnMachineFunction()
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D | PTXInstrInfo.cpp | 57 if (map[i].cls == MRI.getRegClass(DstReg)) { in copyPhysReg() 166 if (!MO.isReg() || RI.getRegClass(MO.getReg()) != &PTX::RegPredRegClass) in DefinesPredicate()
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/external/llvm/utils/TableGen/ |
D | CodeGenTarget.h | 121 return *getRegBank().getRegClass(R); in getRegisterClass()
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/external/llvm/include/llvm/MC/ |
D | MCRegisterInfo.h | 353 const MCRegisterClass getRegClass(unsigned i) const { in getRegClass() function
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonPeephole.cpp | 191 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
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