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Searched refs:SRL (Results 1 – 25 of 57) sorted by relevance

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/external/openssl/crypto/sha/asm/
Dsha512-mips.pl84 $SRL="dsrl"; # shift right logical
98 $SRL="srl"; # shift right logical
159 $SRL $h,$e,@Sigma1[0]
163 $SRL $tmp0,$e,@Sigma1[1]
167 $SRL $tmp0,$e,@Sigma1[2]
174 $SRL $h,$a,@Sigma0[0]
179 $SRL $tmp0,$a,@Sigma0[1]
183 $SRL $tmp0,$a,@Sigma0[2]
210 $SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i)
213 $SRL $tmp0,@X[1],@sigma0[1]
[all …]
Dsha512-sparcv9.pl59 $SRL="srlx"; # shift right logical
85 $SRL="srl"; # shift right logical
222 $SRL $e,@Sigma1[0],$h !! $i
226 $SRL $e,@Sigma1[1],$tmp0
230 $SRL $e,@Sigma1[2],$tmp0
237 $SRL $a,@Sigma0[0],$h
242 $SRL $a,@Sigma0[1],$tmp0
246 $SRL $a,@Sigma0[2],$tmp0
/external/libffi/src/mips/
Dn32.S119 SRL t4, t6, 1*FFI_FLAG_BITS
132 SRL t4, t6, 2*FFI_FLAG_BITS
145 SRL t4, t6, 3*FFI_FLAG_BITS
158 SRL t4, t6, 4*FFI_FLAG_BITS
171 SRL t4, t6, 5*FFI_FLAG_BITS
184 SRL t4, t6, 6*FFI_FLAG_BITS
197 SRL t4, t6, 7*FFI_FLAG_BITS
219 SRL t6, 8*FFI_FLAG_BITS
Dffitarget.h128 # define SRL srl macro
135 # define SRL dsrl
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; in PromoteIntegerResult()
270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
567 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); in PromoteIntRes_SRL()
663 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, in PromoteIntRes_XMULO()
788 case ISD::SRL: in PromoteIntegerOperand()
1154 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; in ExpandIntegerResult()
1293 DAG.getNode(ISD::SRL, DL, NVT, InL, in ExpandShiftByConstant()
1299 if (N->getOpcode() == ISD::SRL) { in ExpandShiftByConstant()
1304 Lo = DAG.getNode(ISD::SRL, DL, in ExpandShiftByConstant()
1312 DAG.getNode(ISD::SRL, DL, NVT, InL, in ExpandShiftByConstant()
[all …]
DTargetLowering.cpp1429 if (InOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
1437 Opc = ISD::SRL; in SimplifyDemandedBits()
1479 case ISD::SRL: in SimplifyDemandedBits()
1497 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
1530 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), in SimplifyDemandedBits()
1562 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
1726 case ISD::SRL: in SimplifyDemandedBits()
1730 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) in SimplifyDemandedBits()
1754 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, in SimplifyDemandedBits()
1884 if (Val.getOpcode() == ISD::SRL) in ValueHasExactlyOneBitSet()
[all …]
DDAGCombiner.cpp873 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1114 case ISD::SRL: return visitSRL(N); in visit()
1197 case ISD::SRL: in combine()
1881 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, in visitSDIV() local
1884 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); in visitSDIV()
1885 AddToWorkList(SRL.getNode()); in visitSDIV()
1935 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, in visitUDIV()
1949 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); in visitUDIV()
2093 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
2129 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHU()
[all …]
DLegalizeDAG.cpp397 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
789 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
800 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
1258 case ISD::SRL: in LegalizeOp()
2120 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, in ExpandLegalINT_TO_FP()
2141 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); in ExpandLegalINT_TO_FP()
2175 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, in ExpandLegalINT_TO_FP()
2328 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); in ExpandBSWAP()
2333 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); in ExpandBSWAP()
2334 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); in ExpandBSWAP()
[all …]
DLegalizeVectorOps.cpp189 case ISD::SRL: in LegalizeOp()
550 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) in ExpandUINT_TO_FLOAT()
570 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord); in ExpandUINT_TO_FLOAT()
/external/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp367 } else if (Opcode == ISD::SRL) { in isRotateAndMask()
414 Op0.getOperand(0).getOpcode() == ISD::SRL) { in SelectBitfieldInsert()
416 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
422 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { in SelectBitfieldInsert()
424 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
435 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && in SelectBitfieldInsert()
442 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && in SelectBitfieldInsert()
1047 case ISD::SRL: { in Select()
DPPCISelLowering.h91 SRL, SRA, SHL, enumerator
/external/llvm/lib/Target/CellSPU/
DSPUNodes.td86 // Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
88 def SPUvec_srl: SDNode<"ISD::SRL", SPUvecshift_type, []>;
DSPUISelLowering.cpp243 setOperationAction(ISD::SRL, MVT::i8, Custom); in SPUTargetLowering()
248 setOperationAction(ISD::SRL, MVT::i64, Legal); in SPUTargetLowering()
2255 case ISD::SRL: in LowerI8Math()
2399 DAG.getNode(ISD::SRL, dl, MVT::i16, in LowerCTPOP()
2430 DAG.getNode(ISD::SRL, dl, MVT::i32, in LowerCTPOP()
2442 DAG.getNode(ISD::SRL, dl, MVT::i32, in LowerCTPOP()
2535 DAG.getNode(ISD::SRL, dl, IntVT, in LowerSETCC()
2569 DAG.getNode(ISD::SRL, dl, IntVT, in LowerSETCC()
2815 case ISD::SRL: in LowerOperation()
DSPUISelDAGToDAG.cpp742 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL) in Select()
764 if (Op0.getOpcode() == ISD::SRL) in Select()
778 } else if (Opc == ISD::SRL) { in Select()
/external/v8/src/mips/
Dconstants-mips.cc244 case SRL: in InstructionType()
Dconstants-mips.h305 SRL = ((0 << 3) + 2), enumerator
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp97 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
100 setOperationAction(ISD::SRL, MVT::i16, Custom); in MSP430TargetLowering()
184 case ISD::SRL: in LowerOperation()
607 case ISD::SRL: in LowerShifts()
608 return DAG.getNode(MSP430ISD::SRL, dl, in LowerShifts()
619 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
DMSP430ISelLowering.h65 SHL, SRA, SRL enumerator
/external/openssl/crypto/bn/asm/
Dmips.pl62 $SRL="dsrl";
77 $SRL="srl";
903 $SRL $at,$a1,$t1
917 $SRL $DH,$a2,4*$BNSZ # bits
925 $SRL $HH,$a0,4*$BNSZ # bits
926 $SRL $QT,4*$BNSZ # q=0xffffffff
933 $SRL $at,$a1,4*$BNSZ # bits
958 $SRL $HH,$a0,4*$BNSZ # bits
959 $SRL $QT,4*$BNSZ # q=0xffffffff
966 $SRL $at,$a1,4*$BNSZ # bits
[all …]
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h316 SHL, SRA, SRL, ROTL, ROTR, enumerator
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp653 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) in PerformANDCombine()
1845 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in LowerFCOPYSIGN32()
1846 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); in LowerFCOPYSIGN32()
1892 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); in LowerFCOPYSIGN64()
1893 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, in LowerFCOPYSIGN64()
1933 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in LowerFABS32()
1958 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); in LowerFABS64()
2037 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, in LowerShiftLeftParts()
2039 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, in LowerShiftLeftParts()
2078 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); in LowerShiftRightParts()
[all …]
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp755 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
986 setOperationAction(ISD::SRL, MVT::v8i16, Custom); in X86TargetLowering()
987 setOperationAction(ISD::SRL, MVT::v16i8, Custom); in X86TargetLowering()
996 setOperationAction(ISD::SRL, MVT::v2i64, Legal); in X86TargetLowering()
997 setOperationAction(ISD::SRL, MVT::v4i32, Legal); in X86TargetLowering()
1004 setOperationAction(ISD::SRL, MVT::v2i64, Custom); in X86TargetLowering()
1005 setOperationAction(ISD::SRL, MVT::v4i32, Custom); in X86TargetLowering()
1050 setOperationAction(ISD::SRL, MVT::v16i16, Custom); in X86TargetLowering()
1051 setOperationAction(ISD::SRL, MVT::v32i8, Custom); in X86TargetLowering()
1100 setOperationAction(ISD::SRL, MVT::v4i64, Legal); in X86TargetLowering()
[all …]
DX86ISelDAGToDAG.cpp751 if (Shift.getOpcode() != ISD::SRL || in FoldMaskAndShiftToExtract()
765 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); in FoldMaskAndShiftToExtract()
861 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() || in FoldMaskAndShiftToScale()
918 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt); in FoldMaskAndShiftToScale()
1027 case ISD::SRL: { in MatchAddressRecursively()
1217 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break; in MatchAddressRecursively()
/external/llvm/lib/Target/MBlaze/
DMBlazeInstrFormats.td27 def FRRC : Format<10>; // SEXT8, SEXT16, SRA, SRC, SRL, FLT, FINT, FSQRT

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