| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 247 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
249 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
251 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
265 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
267 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
269 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
283 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
285 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
287 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
289 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
[all …]
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| D | ARMISelLowering.cpp | 111 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
116 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
562 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); in ARMTargetLowering()
595 setTargetDAGCombine(ISD::FP_TO_SINT); in ARMTargetLowering()
832 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
3250 case ISD::FP_TO_SINT: in LowerFP_TO_INT()
5338 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
5375 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
5484 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
5573 case ISD::FP_TO_SINT: in LowerOperation()
[all …]
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| /external/llvm/test/CodeGen/X86/ |
| D | avx-fp2int.ll | 3 ;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate
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| /external/llvm/test/CodeGen/R600/ |
| D | fcmp.ll | 19 ; SET* + FP_TO_SINT
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| /external/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 255 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 }, in getCastInstrCost()
256 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, in getCastInstrCost()
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| D | README-FPStack.txt | 50 FP_TO_SINT when the source operand is already in memory.
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| D | X86ISelLowering.cpp | 295 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); in X86TargetLowering()
300 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); in X86TargetLowering()
301 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); in X86TargetLowering()
304 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); in X86TargetLowering()
306 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); in X86TargetLowering()
308 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); in X86TargetLowering()
309 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); in X86TargetLowering()
808 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in X86TargetLowering()
976 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in X86TargetLowering()
1118 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom); in X86TargetLowering()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 391 FP_TO_SINT, enumerator
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1151 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
1156 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
1161 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
1166 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in HexagonTargetLowering()
1171 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal); in HexagonTargetLowering()
1183 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand); in HexagonTargetLowering()
1238 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand); in HexagonTargetLowering()
1241 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 612 case ISD::FP_TO_SINT: Res = SoftenFloatOp_FP_TO_SINT(N); break; in SoftenFloatOperand()
1244 case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break; in ExpandFloatOperand()
1340 return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res); in ExpandFloatOp_FP_TO_SINT()
1364 DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, in ExpandFloatOp_FP_TO_UINT()
1370 DAG.getNode(ISD::FP_TO_SINT, dl, in ExpandFloatOp_FP_TO_UINT()
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| D | SelectionDAGDumper.cpp | 227 case ISD::FP_TO_SINT: return "fp_to_sint"; in getOperationName()
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| D | LegalizeVectorTypes.cpp | 83 case ISD::FP_TO_SINT: in ScalarizeVectorResult()
539 case ISD::FP_TO_SINT: in SplitVectorResult()
1060 case ISD::FP_TO_SINT: in SplitVectorOperand()
1413 case ISD::FP_TO_SINT: in WidenVectorResult()
2186 case ISD::FP_TO_SINT: in WidenVectorOperand()
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| D | LegalizeDAG.cpp | 2473 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { in PromoteLegalFP_TO_INT()
2474 OpToUse = ISD::FP_TO_SINT; in PromoteLegalFP_TO_INT()
2920 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); in ExpandNode()
2921 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, in ExpandNode()
3781 case ISD::FP_TO_SINT: in PromoteNode()
3783 Node->getOpcode() == ISD::FP_TO_SINT, dl); in PromoteNode()
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| D | LegalizeVectorOps.cpp | 226 case ISD::FP_TO_SINT: in LegalizeOp()
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| D | LegalizeIntegerTypes.cpp | 97 case ISD::FP_TO_SINT: in PromoteIntegerResult()
362 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteIntRes_FP_TO_XINT()
363 NewOpc = ISD::FP_TO_SINT; in PromoteIntRes_FP_TO_XINT()
1118 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; in ExpandIntegerResult()
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| D | FastISel.cpp | 1047 return SelectCast(I, ISD::FP_TO_SINT); in SelectOperator()
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| D | SelectionDAGBuilder.cpp | 2807 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); in visitFPToSI()
3714 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); in expandExp()
4088 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); in expandExp2()
4198 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); in expandPow()
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| /external/llvm/lib/Target/R600/ |
| D | R600ISelLowering.cpp | 45 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand); in R600TargetLowering()
93 setTargetDAGCombine(ISD::FP_TO_SINT); in R600TargetLowering()
998 case ISD::FP_TO_SINT: { in PerformDAGCombine()
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| D | AMDILISelLowering.cpp | 453 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq); in LowerSDIV24()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 234 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in AArch64TargetLowering()
235 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AArch64TargetLowering()
236 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom); in AArch64TargetLowering()
2320 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, true); in LowerOperation()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 722 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1153 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 195 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
285 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
407 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
4653 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : in LowerFP_TO_INT()
5565 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, in LowerOperation()
5672 case ISD::FP_TO_SINT: in ReplaceNodeResults()
6289 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) { in PerformDAGCombine()
6322 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && in PerformDAGCombine()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 1220 case FPToSI: return ISD::FP_TO_SINT; in InstructionOpcodeToISD()
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1291 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1295 code, an ``FP_TO_SINT`` opcode will call the ``LowerFP_TO_SINT`` method:
1301 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 392 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
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