| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 751 SETGE, // 1 X 0 1 1 True if greater than or equal enumerator
763 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; in isSignedIntSetCC()
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| /external/llvm/test/CodeGen/R600/ |
| D | unsupported-cc.ll | 66 ; CHECK: SETGE T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
76 ; CHECK: SETGE T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00)
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 223 case ISD::SETGE: in LowerMinMax()
296 ISD::SETGE); in LowerUDIVREM()
302 ISD::SETGE); in LowerUDIVREM()
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| D | AMDGPUInstructions.td | 63 case ISD::SETGE: return true;}}}]
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| D | R600Instructions.td | 705 0xA, "SETGE",
814 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
1862 def : CND_INT_f32 <CNDGE_INT, SETGE>;
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 179 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
193 case ICmpInst::ICMP_SGE: return ISD::SETGE; in getICmpCondCode()
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| D | TargetLoweringBase.cpp | 599 CCs[RTLIB::OGE_F32] = ISD::SETGE; in InitCmpLibcallCCs()
600 CCs[RTLIB::OGE_F64] = ISD::SETGE; in InitCmpLibcallCCs()
601 CCs[RTLIB::OGE_F128] = ISD::SETGE; in InitCmpLibcallCCs()
|
| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.td | 771 def : Pat<(setcc (i32 GPR:$L), (i32 0), SETGE),
796 def : Pat<(setcc (i32 0), (i32 GPR:$R), SETGE),
825 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETGE),
862 (i32 GPR:$T), (i32 GPR:$F), SETGE),
893 (i32 GPR:$T), (i32 GPR:$F), SETGE),
924 (i32 GPR:$T), (i32 GPR:$F), SETGE),
959 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 0), SETGE), bb:$T),
980 def : Pat<(brcond (setcc (i32 0), (i32 GPR:$R), SETGE), bb:$T),
1001 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETGE), bb:$T),
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| D | MBlazeInstrFPU.td | 163 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETGE),
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSelectCCInfo.td | 63 IntRegs:$fval, SETGE)),
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrCMovSetCC.td | 107 defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>; // signed greater or equal
|
| D | X86ISelLowering.cpp | 3216 case ISD::SETGE: return X86::COND_GE; in TranslateX86CC()
3261 case ISD::SETGE: return X86::COND_AE; in TranslateX86CC()
9278 case ISD::SETGE: Swap = true; // Fallthrough in LowerVSETCC()
9333 case ISD::SETGE: Swap = true; in LowerVSETCC()
10331 CC = ISD::SETGE; in LowerINTRINSIC_WO_CHAIN()
10361 CC = ISD::SETGE; in LowerINTRINSIC_WO_CHAIN()
15148 case ISD::SETGE: in matchIntegerMINMAX()
15166 case ISD::SETGE: in matchIntegerMINMAX()
15258 case ISD::SETGE: in PerformSELECTCombine()
15292 case ISD::SETGE: in PerformSELECTCombine()
[all …]
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 591 case ISD::SETGE: return PPC::PRED_GE; in getPredicateForSetCC()
619 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE in getCRIdxForSetCC()
658 case ISD::SETGE: in getVCmpInst()
827 case ISD::SETGE: in SelectSETCC()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 122 case ISD::SETGE: in softenSetCCOperands()
1248 case ISD::SETGE: in SimplifySetCC()
1404 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
1409 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); in SimplifySetCC()
1422 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) in SimplifySetCC()
1802 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y in SimplifySetCC()
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| D | SelectionDAGDumper.cpp | 307 case ISD::SETGE: return "setge"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 839 case ISD::SETGE: in PromoteSetCCOperands()
2030 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); in ExpandIntRes_SADDSUBO()
2031 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); in ExpandIntRes_SADDSUBO()
2036 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); in ExpandIntRes_SADDSUBO()
2558 case ISD::SETGE: in IntegerExpandSetCCOperands()
2586 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || in IntegerExpandSetCCOperands()
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| D | LegalizeDAG.cpp | 1645 case ISD::SETGE: in LegalizeSetCCCondCode()
3434 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); in ExpandNode()
3435 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); in ExpandNode()
3440 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); in ExpandNode()
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| D | LegalizeFloatTypes.cpp | 1372 DAG.getCondCode(ISD::SETGE)); in ExpandFloatOp_FP_TO_UINT()
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| D | SelectionDAG.cpp | 260 case ISD::SETGE: return 1; in isSignedOp()
1597 case ISD::SETGE: return getConstant(C1.sge(C2), VT); in FoldSetCC()
1628 case ISD::SETGE: if (R==APFloat::cmpUnordered) in FoldSetCC()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1543 case ISD::SETGE: return A64CC::GE; in IntCCToA64CC()
1591 case ISD::SETGE: in getSelectableIntSetCC()
1607 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getSelectableIntSetCC()
1639 case ISD::SETGE: in FPCCToA64CC()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 654 case ISD::SETGE: return SPCC::ICC_GE; in IntCondCCodeToICC()
677 case ISD::SETGE: in FPCondCCodeToFCC()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 504 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
861 (setcc node:$lhs, node:$rhs, SETGE)>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1142 case ISD::SETGE: return ARMCC::GE; in IntCCToARMCC()
1162 case ISD::SETGE: in FPCCToARMCC()
2854 case ISD::SETGE: in getARMCmp()
2870 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; in getARMCmp()
3515 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, in LowerShiftRightParts()
3549 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, in LowerShiftLeftParts()
3797 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
3830 case ISD::SETGE: Opc = ARMISD::VCGE; break; in LowerVSETCC()
9306 case ISD::SETGE: in PerformSELECT_CCCombine()
9318 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) && in PerformSELECT_CCCombine()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 748 case ISD::SETGE: in EmitCMP()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 984 (setcc node:$lhs, node:$rhs, SETGE)>;
|