Searched refs:SETO (Results 1 – 20 of 20) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 738 SETO, // 0 1 1 1 True if ordered (no nans) enumerator
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrCMovSetCC.td | 94 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set
|
| D | X86ISelLowering.cpp | 3271 case ISD::SETO: return X86::COND_NP; in TranslateX86CC()
9288 case ISD::SETO: SSECC = 7; break; in LowerVSETCC()
|
| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 159 case FCmpInst::FCMP_ORD: return ISD::SETO; in getFCmpCondCode()
|
| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 209 case ISD::SETO: in LowerMinMax()
|
| D | R600Instructions.td | 1940 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1946 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETO),
|
| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrFPU.td | 204 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETO),
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 296 case ISD::SETO: return "seto"; in getOperationName()
|
| D | TargetLowering.cpp | 146 case ISD::SETO: in softenSetCCOperands()
1567 if (Cond == ISD::SETO || Cond == ISD::SETUO) in SimplifySetCC()
1633 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; in SimplifySetCC()
|
| D | LegalizeDAG.cpp | 1611 case ISD::SETO: in LegalizeSetCCCondCode()
1637 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO; in LegalizeSetCCCondCode()
1662 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) { in LegalizeSetCCCondCode()
|
| D | SelectionDAG.cpp | 1573 case ISD::SETO: in FoldSetCC()
1633 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT); in FoldSetCC()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 592 case ISD::SETO: return PPC::PRED_NU; in getPredicateForSetCC()
624 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO in getCRIdxForSetCC()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1279 setCondCodeAction(ISD::SETO, MVT::f64, Expand); in HexagonTargetLowering()
1282 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in HexagonTargetLowering()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 500 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
841 (setcc node:$lhs, node:$rhs, SETO)>;
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 684 case ISD::SETO: return SPCC::FCC_O; in FPCondCCodeToFCC()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 964 (setcc node:$lhs, node:$rhs, SETO)>;
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1644 case ISD::SETO: CondCode = A64CC::VC; break; in FPCCToA64CC()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 639 case ISD::SETO: return Mips::FCOND_OR; in FPCondCCodeToFCC()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1167 case ISD::SETO: CondCode = ARMCC::VC; break; in FPCCToARMCC()
3812 case ISD::SETO: in LowerVSETCC()
|
| /external/srec/config/en.us/dictionary/ |
| D | c0.6 | 102662 SETO S EH1 T OW0
|