| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 155 case FCmpInst::FCMP_OGE: return ISD::SETOGE; in getFCmpCondCode()
179 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 734 SETOGE, // 0 0 1 1 True if ordered and greater than or equal enumerator
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| /external/llvm/lib/Target/R600/ |
| D | AMDILISelLowering.cpp | 122 setOperationAction(ISD::SETOGE, VT, Expand); in InitAMDILLowering()
464 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE); in LowerSDIV24()
466 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE); in LowerSDIV24()
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| D | AMDGPUInstructions.td | 62 case ISD::SETOGE: case ISD::SETUGE:
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| D | AMDGPUISelLowering.cpp | 225 case ISD::SETOGE: in LowerMinMax()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 577 case ISD::SETOGE: in getPredicateForSetCC()
626 case ISD::SETOGE: in getCRIdxForSetCC()
689 case ISD::SETOGE: in getVCmpInst()
828 case ISD::SETOGE: in SelectSETCC()
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| D | PPCISelLowering.cpp | 276 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in PPCTargetLowering()
277 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in PPCTargetLowering()
4594 case ISD::SETOGE: in LowerSELECT_CC()
4619 case ISD::SETOGE: in LowerSELECT_CC()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1132 setCondCodeAction(ISD::SETOGE, MVT::f32, Legal); in HexagonTargetLowering()
1133 setCondCodeAction(ISD::SETOGE, MVT::f64, Legal); in HexagonTargetLowering()
1226 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in HexagonTargetLowering()
1229 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrFPU.td | 175 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOGE),
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 291 case ISD::SETOGE: return "setoge"; in getOperationName()
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| D | TargetLowering.cpp | 123 case ISD::SETOGE: in softenSetCCOperands()
1592 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) in SimplifySetCC()
1593 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE); in SimplifySetCC()
1595 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType())) in SimplifySetCC()
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| D | SelectionDAG.cpp | 1569 case ISD::SETOGE: in FoldSetCC()
1631 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan || in FoldSetCC()
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| D | LegalizeDAG.cpp | 1623 case ISD::SETOGE: in LegalizeSetCCCondCode()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 499 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
833 (setcc node:$lhs, node:$rhs, SETOGE)>;
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 678 case ISD::SETOGE: return SPCC::FCC_GE; in FPCondCCodeToFCC()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1163 case ISD::SETOGE: CondCode = ARMCC::GE; break; in FPCCToARMCC()
3796 case ISD::SETOGE: in LowerVSETCC()
9304 case ISD::SETOGE: in PerformSELECT_CCCombine()
9318 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) && in PerformSELECT_CCCombine()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 956 (setcc node:$lhs, node:$rhs, SETOGE)>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1640 case ISD::SETOGE: CondCode = A64CC::GE; break; in FPCCToA64CC()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 633 case ISD::SETOGE: return Mips::FCOND_OGE; in FPCondCCodeToFCC()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3260 case ISD::SETOGE: in TranslateX86CC()
9277 case ISD::SETOGE: in LowerVSETCC()
15232 case ISD::SETOGE: in PerformSELECTCombine()
15267 case ISD::SETOGE: in PerformSELECTCombine()
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