| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 157 case FCmpInst::FCMP_OLE: return ISD::SETOLE; in getFCmpCondCode()
177 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE; in getFCmpCodeWithoutNaN()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 736 SETOLE, // 0 1 0 1 True if ordered and less than or equal enumerator
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 576 case ISD::SETOLE: in getPredicateForSetCC()
627 case ISD::SETOLE: in getCRIdxForSetCC()
685 case ISD::SETOLE: in getVCmpInst()
843 case ISD::SETOLE: in SelectSETCC()
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| D | PPCISelLowering.cpp | 278 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in PPCTargetLowering()
279 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); in PPCTargetLowering()
4602 case ISD::SETOLE: in LowerSELECT_CC()
4631 case ISD::SETOLE: in LowerSELECT_CC()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUInstructions.td | 76 case ISD::SETOLE: case ISD::SETULE:
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| D | AMDGPUISelLowering.cpp | 213 case ISD::SETOLE: in LowerMinMax()
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| D | AMDILISelLowering.cpp | 124 setOperationAction(ISD::SETOLE, VT, Expand); in InitAMDILLowering()
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| D | R600ISelLowering.cpp | 597 case ISD::SETOLE: in LowerSELECT_CC()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1142 setCondCodeAction(ISD::SETOLE, MVT::f32, Legal); in HexagonTargetLowering()
1143 setCondCodeAction(ISD::SETOLE, MVT::f64, Legal); in HexagonTargetLowering()
1244 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); in HexagonTargetLowering()
1247 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrFPU.td | 178 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETOLE),
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 293 case ISD::SETOLE: return "setole"; in getOperationName()
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| D | TargetLowering.cpp | 133 case ISD::SETOLE: in softenSetCCOperands()
1579 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) in SimplifySetCC()
1580 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE); in SimplifySetCC()
1582 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType())) in SimplifySetCC()
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| D | SelectionDAG.cpp | 1571 case ISD::SETOLE: in FoldSetCC()
1626 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan || in FoldSetCC()
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| D | LegalizeDAG.cpp | 1625 case ISD::SETOLE: in LegalizeSetCCCondCode()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 499 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
837 (setcc node:$lhs, node:$rhs, SETOLE)>;
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 676 case ISD::SETOLE: return SPCC::FCC_LE; in FPCondCCodeToFCC()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1165 case ISD::SETOLE: CondCode = ARMCC::LS; break; in FPCCToARMCC()
3794 case ISD::SETOLE: in LowerVSETCC()
9282 case ISD::SETOLE: in PerformSELECT_CCCombine()
9296 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && in PerformSELECT_CCCombine()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 960 (setcc node:$lhs, node:$rhs, SETOLE)>;
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1642 case ISD::SETOLE: CondCode = A64CC::LS; break; in FPCCToA64CC()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 3239 case ISD::SETOLE: in TranslateX86CC()
3259 case ISD::SETOLE: // flipped in TranslateX86CC()
9280 case ISD::SETOLE: SSECC = 2; break; in LowerVSETCC()
15214 case ISD::SETOLE: in PerformSELECTCombine()
15302 case ISD::SETOLE: in PerformSELECTCombine()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 631 case ISD::SETOLE: return Mips::FCOND_OLE; in FPCondCCodeToFCC()
|