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Searched refs:SrcReg (Results 1 – 25 of 76) sorted by relevance

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/external/llvm/lib/Target/R600/
DSIInstrInfo.cpp37 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
43 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); in copyPhysReg()
69 assert(AMDGPU::SReg_32RegClass.contains(SrcReg)); in copyPhysReg()
71 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
75 assert(AMDGPU::SReg_64RegClass.contains(SrcReg)); in copyPhysReg()
77 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
81 assert(AMDGPU::SReg_128RegClass.contains(SrcReg)); in copyPhysReg()
86 assert(AMDGPU::SReg_256RegClass.contains(SrcReg)); in copyPhysReg()
91 assert(AMDGPU::SReg_512RegClass.contains(SrcReg)); in copyPhysReg()
96 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) || in copyPhysReg()
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/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp82 unsigned &SrcReg, unsigned &DstReg, in isCoalescableExtInstr() argument
88 SrcReg = MI.getOperand(1).getReg(); in isCoalescableExtInstr()
410 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
413 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
415 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
417 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
419 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
421 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
423 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
431 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
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DPPCInstrInfo.h72 unsigned SrcReg, bool isKill, int FrameIdx,
98 unsigned &SrcReg, unsigned &DstReg,
125 unsigned DestReg, unsigned SrcReg,
130 unsigned SrcReg, bool isKill, int FrameIndex,
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp38 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
41 NVPTX::Int32RegsRegClass.contains(SrcReg)) in copyPhysReg()
43 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
45 NVPTX::Int8RegsRegClass.contains(SrcReg)) in copyPhysReg()
47 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
49 NVPTX::Int1RegsRegClass.contains(SrcReg)) in copyPhysReg()
51 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
53 NVPTX::Float32RegsRegClass.contains(SrcReg)) in copyPhysReg()
55 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
57 NVPTX::Int16RegsRegClass.contains(SrcReg)) in copyPhysReg()
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/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp43 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
46 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg()
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
53 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
57 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && in storeRegToStackSlot()
58 isARMLowRegister(SrcReg))) && "Unknown regclass!"); in storeRegToStackSlot()
61 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && in storeRegToStackSlot()
62 isARMLowRegister(SrcReg))) { in storeRegToStackSlot()
74 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
DARMBaseInstrInfo.cpp654 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
657 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); in copyPhysReg()
661 .addReg(SrcReg, getKillRegState(KillSrc)))); in copyPhysReg()
666 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); in copyPhysReg()
675 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
677 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
682 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
684 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
695 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
697 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
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DThumb1InstrInfo.h44 unsigned DestReg, unsigned SrcReg,
48 unsigned SrcReg, bool isKill, int FrameIndex,
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp87 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
92 if (Mips::CPURegsRegClass.contains(SrcReg)) in copyPhysReg()
94 else if (Mips::CCRRegClass.contains(SrcReg)) in copyPhysReg()
96 else if (Mips::FGR32RegClass.contains(SrcReg)) in copyPhysReg()
98 else if (SrcReg == Mips::HI) in copyPhysReg()
99 Opc = Mips::MFHI, SrcReg = 0; in copyPhysReg()
100 else if (SrcReg == Mips::LO) in copyPhysReg()
101 Opc = Mips::MFLO, SrcReg = 0; in copyPhysReg()
103 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg. in copyPhysReg()
113 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
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DMips16InstrInfo.cpp70 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
75 Mips::CPURegsRegClass.contains(SrcReg)) in copyPhysReg()
78 Mips::CPU16RegsRegClass.contains(SrcReg)) in copyPhysReg()
80 else if ((SrcReg == Mips::HI) && in copyPhysReg()
82 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
84 else if ((SrcReg == Mips::LO) && in copyPhysReg()
86 Opc = Mips::Mflo16, SrcReg = 0; in copyPhysReg()
96 if (SrcReg) in copyPhysReg()
97 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
102 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
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/external/llvm/lib/CodeGen/
DStrongPHIElimination.cpp249 unsigned SrcReg = SrcMO.getReg(); in runOnMachineFunction() local
250 addReg(SrcReg); in runOnMachineFunction()
251 unionRegs(DestReg, SrcReg); in runOnMachineFunction()
253 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in runOnMachineFunction()
291 unsigned SrcReg = BBI->getOperand(i).getReg(); in runOnMachineFunction() local
292 addReg(SrcReg); in runOnMachineFunction()
293 unionRegs(DestReg, SrcReg); in runOnMachineFunction()
308 unsigned SrcReg = PHI->getOperand(1).getReg(); in runOnMachineFunction() local
309 unsigned SrcColor = getRegColor(SrcReg); in runOnMachineFunction()
312 NewReg = SrcReg; in runOnMachineFunction()
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DPHIElimination.cpp354 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg(); in LowerPHINode() local
357 isImplicitlyDefined(SrcReg, MRI); in LowerPHINode()
358 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && in LowerPHINode()
374 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg); in LowerPHINode()
388 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerPHINode()
394 .addReg(SrcReg, 0, SrcSubReg); in LowerPHINode()
402 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] && in LowerPHINode()
403 !LV->isLiveOut(SrcReg, opBlock)) { in LowerPHINode()
424 if (Term->readsRegister(SrcReg)) in LowerPHINode()
438 if (KillInst->readsRegister(SrcReg)) in LowerPHINode()
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DRegisterCoalescer.h36 unsigned SrcReg; variable
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), in CoalescerPair()
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), in CoalescerPair()
105 unsigned getSrcReg() const { return SrcReg; } in getSrcReg()
DPeepholeOptimizer.cpp150 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
151 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
155 TargetRegisterInfo::isPhysicalRegister(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
158 if (MRI->hasOneNonDBGUse(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
175 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; in INITIALIZE_PASS_DEPENDENCY()
193 UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end(); in INITIALIZE_PASS_DEPENDENCY()
269 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
381 unsigned SrcReg, SrcReg2; in optimizeCmpInstr() local
383 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
384 TargetRegisterInfo::isPhysicalRegister(SrcReg) || in optimizeCmpInstr()
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DTwoAddressInstructionPass.cpp333 unsigned &SrcReg, unsigned &DstReg, in isCopyToReg() argument
335 SrcReg = 0; in isCopyToReg()
339 SrcReg = MI.getOperand(1).getReg(); in isCopyToReg()
342 SrcReg = MI.getOperand(2).getReg(); in isCopyToReg()
346 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); in isCopyToReg()
417 unsigned SrcReg, DstReg; in isKilled() local
420 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled()
422 Reg = SrcReg; in isKilled()
459 unsigned SrcReg; in findOnlyInterestingUse() local
461 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) { in findOnlyInterestingUse()
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DOptimizePHIs.cpp99 unsigned SrcReg = MI->getOperand(i).getReg(); in IsSingleValuePHICycle() local
100 if (SrcReg == DstReg) in IsSingleValuePHICycle()
102 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
120 SingleValReg = SrcReg; in IsSingleValuePHICycle()
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp134 unsigned SrcReg = Src.getReg(); in runOnMachineFunction() local
137 TargetRegisterInfo::isVirtualRegister(SrcReg)) { in runOnMachineFunction()
141 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
158 unsigned SrcReg = Src1.getReg(); in runOnMachineFunction() local
160 std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/); in runOnMachineFunction()
170 unsigned SrcReg = Src.getReg(); in runOnMachineFunction() local
173 TargetRegisterInfo::isVirtualRegister(SrcReg)) { in runOnMachineFunction()
177 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
193 unsigned SrcReg = Src.getReg(); in runOnMachineFunction() local
195 TargetRegisterInfo::isVirtualRegister(SrcReg)) { in runOnMachineFunction()
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DHexagonExpandPredSpillCode.cpp85 int SrcReg = MI->getOperand(2).getReg(); in runOnMachineFunction() local
86 assert(Hexagon::PredRegsRegClass.contains(SrcReg) && in runOnMachineFunction()
97 HEXAGON_RESERVED_REG_2).addReg(SrcReg); in runOnMachineFunction()
106 HEXAGON_RESERVED_REG_2).addReg(SrcReg); in runOnMachineFunction()
115 HEXAGON_RESERVED_REG_2).addReg(SrcReg); in runOnMachineFunction()
DHexagonInstrInfo.h70 unsigned &SrcReg, unsigned &SrcReg2,
75 unsigned DestReg, unsigned SrcReg,
80 unsigned SrcReg, bool isKill, int FrameIndex,
84 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp43 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
47 if (DestReg == AArch64::XSP || SrcReg == AArch64::XSP) { in copyPhysReg()
50 .addReg(SrcReg) in copyPhysReg()
53 } else if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) { in copyPhysReg()
56 .addReg(SrcReg) in copyPhysReg()
60 assert(AArch64::GPR64RegClass.contains(SrcReg)); in copyPhysReg()
64 .addReg(SrcReg); in copyPhysReg()
65 } else if (SrcReg == AArch64::NZCV) { in copyPhysReg()
71 assert(AArch64::GPR64RegClass.contains(SrcReg)); in copyPhysReg()
75 assert(AArch64::GPR32RegClass.contains(SrcReg)); in copyPhysReg()
[all …]
DAArch64InstrInfo.h43 unsigned DestReg, unsigned SrcReg,
52 unsigned SrcReg, bool isKill, int FrameIndex,
101 unsigned DstReg, unsigned SrcReg, unsigned ScratchReg,
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp282 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
284 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
286 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
287 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
289 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
290 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
292 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
299 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
308 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot()
311 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp36 unsigned SrcReg, bool isKill, int FrameIdx, in storeRegToStackSlot() argument
53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
90 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
101 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp336 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
339 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg); in copyPhysReg()
343 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
348 if (GRDest && SrcReg == XCore::SP) { in copyPhysReg()
355 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
363 unsigned SrcReg, bool isKill, in storeRegToStackSlot() argument
371 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp85 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { in EmitCopyFromReg() argument
87 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { in EmitCopyFromReg()
92 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; in EmitCopyFromReg()
120 } else if (DestReg != SrcReg) in EmitCopyFromReg()
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); in EmitCopyFromReg()
172 VRBase = SrcReg; in EmitCopyFromReg()
177 VRBase).addReg(SrcReg); in EmitCopyFromReg()
481 unsigned SrcReg, DstReg, DefSubIdx; in EmitSubregNode() local
483 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && in EmitSubregNode()
485 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
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/external/llvm/lib/Target/X86/
DX86InstrInfo.h171 unsigned &SrcReg, unsigned &DstReg,
235 unsigned DestReg, unsigned SrcReg,
239 unsigned SrcReg, bool isKill, int FrameIndex,
243 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
382 virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
389 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,

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