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Searched refs:BaseReg (Results 1 – 25 of 30) sorted by relevance

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/external/llvm/lib/Target/ARM/
DThumb1RegisterInfo.cpp93 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg() argument
100 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
112 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
170 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmediate() argument
186 if (DestReg == BaseReg && BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
192 } else if (!isSub && BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
208 if (DestReg != BaseReg) in emitThumbRegPlusImmediate()
230 DestReg, BaseReg, NumBytes, true, in emitThumbRegPlusImmediate()
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DThumb2InstrInfo.cpp179 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
187 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
209 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
216 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
227 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
230 .addReg(BaseReg).setMIFlags(MIFlags)); in emitT2RegPlusImmediate()
231 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
236 if (BaseReg == ARM::SP) { in emitT2RegPlusImmediate()
242 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags)); in emitT2RegPlusImmediate()
260 assert(DestReg != ARM::SP && BaseReg != ARM::SP); in emitT2RegPlusImmediate()
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DARMLoadStoreOptimizer.cpp1077 unsigned BaseReg, bool BaseKill, bool BaseUndef, in InsertLDR_STR() argument
1085 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1091 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1103 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() local
1110 bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3(); in FixInvalidRegPairOp()
1140 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1147 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1171 (TRI->regsOverlap(EvenReg, BaseReg))) { in FixInvalidRegPairOp()
1172 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1175 BaseReg, false, BaseUndef, false, OffUndef, in FixInvalidRegPairOp()
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DARMBaseRegisterInfo.h132 unsigned BaseReg, int FrameIdx,
135 unsigned BaseReg, int64_t Offset) const;
DARMBaseRegisterInfo.cpp542 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister() argument
556 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
558 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
567 unsigned BaseReg, int64_t Offset) const { in resolveFrameIndex() argument
584 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
587 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
DThumb2SizeReduction.cpp391 unsigned BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
392 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA) in ReduceLoadStore()
399 if (MI->getOperand(i).getReg() == BaseReg) { in ReduceLoadStore()
413 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
414 if (BaseReg != ARM::SP) in ReduceLoadStore()
427 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
428 if (BaseReg == ARM::SP && in ReduceLoadStore()
433 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()
DARMBaseInstrInfo.h384 unsigned DestReg, unsigned BaseReg, int NumBytes,
390 unsigned DestReg, unsigned BaseReg, int NumBytes,
395 unsigned DestReg, unsigned BaseReg,
DThumb1RegisterInfo.h53 unsigned BaseReg, int64_t Offset) const;
DARMConstantIslandPass.cpp1879 unsigned BaseReg = MI->getOperand(0).getReg(); in optimizeThumb2JumpTables() local
1891 while (PrevI != B && !PrevI->definesRegister(BaseReg)) in optimizeThumb2JumpTables()
1896 if (!PrevI->definesRegister(BaseReg)) in optimizeThumb2JumpTables()
1908 if (MO.isDef() && MO.getReg() != BaseReg) { in optimizeThumb2JumpTables()
1922 for (--PrevI; PrevI != B && !PrevI->definesRegister(BaseReg); --PrevI) in optimizeThumb2JumpTables()
1930 LeaMI->getOperand(0).getReg() != BaseReg) in optimizeThumb2JumpTables()
DARMBaseInstrInfo.cpp159 unsigned BaseReg = Base.getReg(); in convertToThreeAddress() local
175 .addReg(BaseReg).addImm(Amt) in convertToThreeAddress()
182 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) in convertToThreeAddress()
187 .addReg(BaseReg).addReg(OffReg) in convertToThreeAddress()
198 .addReg(BaseReg).addImm(Amt) in convertToThreeAddress()
203 .addReg(BaseReg).addReg(OffReg) in convertToThreeAddress()
225 .addReg(BaseReg).addImm(0).addImm(Pred); in convertToThreeAddress()
229 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); in convertToThreeAddress()
1776 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitARMRegPlusImmediate() argument
1795 .addReg(BaseReg, RegState::Kill).addImm(ThisVal) in emitARMRegPlusImmediate()
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/external/llvm/lib/CodeGen/
DLocalStackSlotAllocation.cpp290 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
310 BaseReg = RegOffset.first; in insertFrameReferenceRegisters()
319 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); in insertFrameReferenceRegisters()
321 DEBUG(dbgs() << " Materializing base register " << BaseReg << in insertFrameReferenceRegisters()
328 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, in insertFrameReferenceRegisters()
339 std::pair<unsigned, int64_t>(BaseReg, BaseOffset)); in insertFrameReferenceRegisters()
343 assert(BaseReg != 0 && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
347 TRI->resolveFrameIndex(I, BaseReg, Offset); in insertFrameReferenceRegisters()
DMachineScheduler.cpp757 unsigned BaseReg; member
760 : SU(su), BaseReg(reg), Offset(ofs) {} in LoadInfo()
781 if (LHS.BaseReg != RHS.BaseReg) in LoadInfoLess()
782 return LHS.BaseReg < RHS.BaseReg; in LoadInfoLess()
791 unsigned BaseReg; in clusterNeighboringLoads() local
793 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI)) in clusterNeighboringLoads()
794 LoadRecords.push_back(LoadInfo(SU, BaseReg, Offset)); in clusterNeighboringLoads()
801 if (LoadRecords[Idx].BaseReg != LoadRecords[Idx+1].BaseReg) { in clusterNeighboringLoads()
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.cpp139 unsigned BaseReg = in eliminateFrameIndex() local
142 BaseReg, FrameReg, BaseReg, Offset); in eliminateFrameIndex()
143 FrameReg = BaseReg; in eliminateFrameIndex()
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp190 unsigned BaseReg; member
254 return Mem.BaseReg; in getMemBaseReg()
507 Res->Mem.BaseReg = 0; in CreateMem()
518 unsigned BaseReg, unsigned IndexReg, in CreateMem()
523 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!"); in CreateMem()
531 Res->Mem.BaseReg = BaseReg; in CreateMem()
550 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0); in isSrcOp()
560 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0; in isDstOp()
710 unsigned BaseReg, IndexReg, Scale; member in IntelBracExprStateMachine
720 State(IBES_START), BaseReg(0), IndexReg(0), Scale(1), Disp(0), in IntelBracExprStateMachine()
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/external/llvm/lib/Target/X86/InstPrinter/
DX86ATTInstPrinter.cpp176 const MCOperand &BaseReg = MI->getOperand(Op); in printMemReference() local
191 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
198 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
200 if (BaseReg.getReg()) in printMemReference()
DX86IntelInstPrinter.cpp160 const MCOperand &BaseReg = MI->getOperand(Op); in printMemReference() local
175 if (BaseReg.getReg()) { in printMemReference()
194 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
/external/llvm/lib/Target/X86/
DX86CodeEmitter.cpp489 unsigned BaseReg = Base.getReg(); in emitMemModRMByte() local
492 if (BaseReg == X86::RIP || in emitMemModRMByte()
511 if (BaseReg != 0 && BaseReg != X86::RIP) in emitMemModRMByte()
512 BaseRegNo = getX86RegNum(BaseReg); in emitMemModRMByte()
522 (!Is64BitMode || BaseReg != 0)) { in emitMemModRMByte()
523 if (BaseReg == 0 || // [disp32] in X86-32 mode in emitMemModRMByte()
524 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode in emitMemModRMByte()
558 if (BaseReg == 0) { in emitMemModRMByte()
583 if (BaseReg == 0) { in emitMemModRMByte()
593 unsigned BaseRegNo = getX86RegNum(BaseReg); in emitMemModRMByte()
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DX86AsmPrinter.cpp272 const MachineOperand &BaseReg = MI->getOperand(Op); in printLeaMemReference() local
277 bool HasBaseReg = BaseReg.getReg() != 0; in printLeaMemReference()
279 BaseReg.getReg() == X86::RIP) in printLeaMemReference()
331 const MachineOperand &BaseReg = MI->getOperand(Op); in printIntelMemReference() local
346 if (BaseReg.getReg()) { in printIntelMemReference()
364 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printIntelMemReference()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp167 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
170 if ((BaseReg.getReg() != 0 && in Is32BitMemOperand()
171 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in Is32BitMemOperand()
182 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
185 if ((BaseReg.getReg() != 0 && in Is64BitMemOperand()
186 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || in Is64BitMemOperand()
197 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
200 if ((BaseReg.getReg() != 0 && in Is16BitMemOperand()
201 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || in Is16BitMemOperand()
307 unsigned BaseReg = Base.getReg(); in EmitMemModRMByte() local
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/external/llvm/lib/Transforms/Scalar/
DCodeGenPrepare.cpp827 Value *BaseReg; member
829 ExtAddrMode() : BaseReg(0), ScaledReg(0) {} in ExtAddrMode()
834 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) && in operator ==()
858 if (BaseReg) { in print()
861 WriteAsOperand(OS, BaseReg, /*PrintType=*/false); in print()
1146 AddrMode.BaseReg = AddrInst->getOperand(0); in MatchOperationAddr()
1159 AddrMode.BaseReg = AddrInst->getOperand(0); in MatchOperationAddr()
1227 AddrMode.BaseReg = Addr; in MatchAddr()
1232 AddrMode.BaseReg = 0; in MatchAddr()
1382 Value *BaseReg = AMAfter.BaseReg, *ScaledReg = AMAfter.ScaledReg; in IsProfitableToFoldIntoAddressingMode() local
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DLoopStrengthReduce.cpp922 const SCEV *BaseReg = *I; in RateFormula() local
923 if (VisitedRegs.count(BaseReg)) { in RateFormula()
927 RatePrimaryRegister(BaseReg, Regs, L, SE, DT, LoserRegs); in RateFormula()
3101 const SCEV *BaseReg = Base.BaseRegs[i]; in GenerateReassociations() local
3104 const SCEV *Remainder = CollectSubexprs(BaseReg, 0, AddOps, L, SE); in GenerateReassociations()
3184 const SCEV *BaseReg = *I; in GenerateCombinations() local
3185 if (SE.properlyDominates(BaseReg, L->getHeader()) && in GenerateCombinations()
3186 !SE.hasComputableLoopEvolution(BaseReg, L)) in GenerateCombinations()
3187 Ops.push_back(BaseReg); in GenerateCombinations()
3189 F.BaseRegs.push_back(BaseReg); in GenerateCombinations()
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/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h716 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister() argument
725 unsigned BaseReg, int64_t Offset) const { in resolveFrameIndex() argument
/external/clang/lib/StaticAnalyzer/Core/
DStore.cpp285 const MemRegion *BaseReg = in evalDerivedToBase() local
289 return loc::MemRegionVal(BaseReg); in evalDerivedToBase()
/external/llvm/lib/Target/R600/
DAMDILISelDAGToDAG.cpp76 SDValue &BaseReg, SDValue& Offset);
572 SDValue& BaseReg, SDValue &Offset) { in SelectGlobalValueVariableOffset() argument
574 BaseReg = Addr; in SelectGlobalValueVariableOffset()
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp228 unsigned BaseReg = MI->getOperand(0).getReg(); in printInst() local
230 if (MI->getOperand(i).getReg() == BaseReg) in printInst()
238 printRegName(O, BaseReg); in printInst()

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