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Searched refs:NewOpc (Results 1 – 21 of 21) sorted by relevance

/external/llvm/lib/Target/X86/
DX86MCInstLower.cpp229 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) { in LowerUnaryToTwoAddr() argument
230 OutMI.setOpcode(NewOpc); in LowerUnaryToTwoAddr()
413 unsigned NewOpc; in Lower() local
416 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break; in Lower()
417 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break; in Lower()
418 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break; in Lower()
419 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break; in Lower()
420 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break; in Lower()
421 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break; in Lower()
422 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break; in Lower()
[all …]
DX86InstrInfo.cpp3534 unsigned NewOpc; in optimizeCompareInstr() local
3536 NewOpc = GetCondBranchFromCond(NewCC); in optimizeCompareInstr()
3538 NewOpc = getSETFromCond(NewCC, HasMemoryOperand); in optimizeCompareInstr()
3541 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), in optimizeCompareInstr()
3548 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); in optimizeCompareInstr()
4029 unsigned NewOpc = 0; in foldMemoryOperandImpl() local
4033 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; in foldMemoryOperandImpl()
4034 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; in foldMemoryOperandImpl()
4035 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; in foldMemoryOperandImpl()
4036 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; in foldMemoryOperandImpl()
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/external/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp776 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) in MergeBaseUpdateLSMultiple()
875 unsigned NewOpc = 0; in MergeBaseUpdateLoadStore() local
893 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub); in MergeBaseUpdateLoadStore()
912 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub); in MergeBaseUpdateLoadStore()
930 BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) in MergeBaseUpdateLoadStore()
939 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { in MergeBaseUpdateLoadStore()
941 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
946 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
953 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) in MergeBaseUpdateLoadStore()
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DThumb2InstrInfo.cpp474 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex() local
475 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
508 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
518 NewOpc = immediateOffsetOpcode(Opcode); in rewriteT2FrameIndex()
530 NewOpc = negativeOffsetOpcode(Opcode); in rewriteT2FrameIndex()
535 NewOpc = positiveOffsetOpcode(Opcode); in rewriteT2FrameIndex()
565 if (NewOpc != Opcode) in rewriteT2FrameIndex()
566 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
599 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
DARMConstantIslandPass.cpp1701 unsigned NewOpc = 0; in optimizeThumb2Instructions() local
1708 NewOpc = ARM::tLEApcrel; in optimizeThumb2Instructions()
1715 NewOpc = ARM::tLDRpci; in optimizeThumb2Instructions()
1722 if (!NewOpc) in optimizeThumb2Instructions()
1735 U.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Instructions()
1755 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1761 NewOpc = ARM::tB; in optimizeThumb2Branches()
1766 NewOpc = ARM::tBcc; in optimizeThumb2Branches()
1772 if (NewOpc) { in optimizeThumb2Branches()
1777 Br.MI->setDesc(TII->get(NewOpc)); in optimizeThumb2Branches()
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DThumb1RegisterInfo.cpp462 unsigned NewOpc = convertToNonSPOpcode(Opcode); in rewriteFrameIndex() local
463 if (NewOpc != Opcode && FrameReg != ARM::SP) in rewriteFrameIndex()
464 MI.setDesc(TII.get(NewOpc)); in rewriteFrameIndex()
DARMISelLowering.cpp2575 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) in LowerINTRINSIC_WO_CHAIN() local
2577 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
5509 unsigned NewOpc = 0; in LowerMUL() local
5514 NewOpc = ARMISD::VMULLs; in LowerMUL()
5519 NewOpc = ARMISD::VMULLu; in LowerMUL()
5524 NewOpc = ARMISD::VMULLs; in LowerMUL()
5527 NewOpc = ARMISD::VMULLu; in LowerMUL()
5531 NewOpc = ARMISD::VMULLu; in LowerMUL()
5536 if (!NewOpc) { in LowerMUL()
5555 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); in LowerMUL()
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DARMExpandPseudoInsts.cpp942 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local
944 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
973 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI() local
975 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
1004 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q : in ExpandMI() local
1007 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMI()
DARMISelDAGToDAG.cpp3172 unsigned NewOpc = isThumb ? ARM::t2LDREXD :ARM::LDREXD; in Select() local
3189 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops); in Select()
3250 unsigned NewOpc = isThumb ? ARM::t2STREXD : ARM::STREXD; in Select() local
3252 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops); in Select()
/external/llvm/lib/Target/R600/
DSIInstrInfo.cpp172 int NewOpc; in commuteOpcode() local
175 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1) in commuteOpcode()
176 return NewOpc; in commuteOpcode()
179 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1) in commuteOpcode()
180 return NewOpc; in commuteOpcode()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.h59 SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
DMipsInstrInfo.cpp278 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc() argument
281 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); in genInstrWithNewOpc()
DMipsInstrInfo.h117 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
DMipsLongBranch.cpp222 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); in replaceBranch() local
223 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
DMipsSEISelLowering.cpp567 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc, in lowerMulDiv() argument
572 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped, in lowerMulDiv()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelDAGToDAG.cpp166 unsigned int NewOpc = AMDGPU::COPY; in Select() local
168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI); in Select()
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DAMDILISelDAGToDAG.cpp166 unsigned int NewOpc = AMDGPU::COPY; in Select() local
168 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, TFI); in Select()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp6767 unsigned NewOpc; in processInstruction() local
6770 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; in processInstruction()
6771 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; in processInstruction()
6772 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; in processInstruction()
6776 TmpInst.setOpcode(NewOpc); in processInstruction()
7241 unsigned NewOpc; in processInstruction() local
7244 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; in processInstruction()
7245 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; in processInstruction()
7246 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; in processInstruction()
7247 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; in processInstruction()
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/external/llvm/lib/CodeGen/
DMachineLICM.cpp1255 unsigned NewOpc = in ExtractHoistableLoad() local
1260 if (NewOpc == 0) return 0; in ExtractHoistableLoad()
1261 const MCInstrDesc &MID = TII->get(NewOpc); in ExtractHoistableLoad()
DTwoAddressInstructionPass.cpp1186 unsigned NewOpc = in tryInstructionTransform() local
1191 if (NewOpc != 0) { in tryInstructionTransform()
1192 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc); in tryInstructionTransform()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp353 unsigned NewOpc = N->getOpcode(); in PromoteIntRes_FP_TO_XINT() local
363 NewOpc = ISD::FP_TO_SINT; in PromoteIntRes_FP_TO_XINT()
365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); in PromoteIntRes_FP_TO_XINT()