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Searched refs:DestReg (Results 1 – 25 of 85) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonSplitTFRCondSets.cpp98 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
114 if (DestReg != SrcReg1) { in runOnMachineFunction()
116 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction()
118 if (DestReg != SrcReg2) { in runOnMachineFunction()
120 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); in runOnMachineFunction()
128 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
133 if (DestReg != SrcReg1) { in runOnMachineFunction()
135 TII->get(Hexagon::TFR_cPt), DestReg). in runOnMachineFunction()
140 TII->get(Hexagon::TFRI_cNotPt), DestReg). in runOnMachineFunction()
145 TII->get(Hexagon::TFRI_cNotPt_f), DestReg). in runOnMachineFunction()
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DHexagonSplitConst32AndConst64.cpp89 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
93 TII->get(Hexagon::LO), DestReg).addOperand(Symbol); in runOnMachineFunction()
95 TII->get(Hexagon::HI), DestReg).addOperand(Symbol); in runOnMachineFunction()
102 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
106 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol); in runOnMachineFunction()
108 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol); in runOnMachineFunction()
115 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
119 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol); in runOnMachineFunction()
121 TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol); in runOnMachineFunction()
128 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
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DHexagonCopyToCombine.cpp93 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
96 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
99 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
102 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
121 unsigned DestReg = MI->getOperand(0).getReg(); in isCombinableInstType() local
123 return Hexagon::IntRegsRegClass.contains(DestReg) && in isCombinableInstType()
131 unsigned DestReg = MI->getOperand(0).getReg(); in isCombinableInstType() local
134 return Hexagon::IntRegsRegClass.contains(DestReg) && in isCombinableInstType()
149 unsigned DestReg = MI->getOperand(0).getReg(); in isCombinableInstType() local
150 return Hexagon::IntRegsRegClass.contains(DestReg); in isCombinableInstType()
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DHexagonInstrInfo.cpp418 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
420 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
421 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg); in copyPhysReg()
424 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
425 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg); in copyPhysReg()
428 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
431 DestReg).addReg(SrcReg).addReg(SrcReg); in copyPhysReg()
434 if (Hexagon::DoubleRegsRegClass.contains(DestReg) && in copyPhysReg()
437 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) { in copyPhysReg()
439 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, in copyPhysReg()
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/external/llvm/lib/Target/ARM/
DThumb1RegisterInfo.cpp65 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool() argument
77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
91 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg() argument
97 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
108 unsigned LdReg = DestReg; in emitThumbRegPlusImmInReg()
109 if (DestReg == ARM::SP) { in emitThumbRegPlusImmInReg()
129 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmInReg()
132 if (DestReg == ARM::SP || isSub) in emitThumbRegPlusImmInReg()
168 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmediate() argument
184 if (DestReg == BaseReg && BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
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DThumb2InstrInfo.cpp115 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
118 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
119 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
121 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
170 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
186 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
196 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in loadRegFromStackSlot()
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
204 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
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DThumb1InstrInfo.cpp42 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
44 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
46 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
80 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
84 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
85 isARMLowRegister(DestReg))) && "Unknown regclass!"); in loadRegFromStackSlot()
88 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
89 isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
100 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) in loadRegFromStackSlot()
DARMBaseInstrInfo.cpp664 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
666 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
670 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
675 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
685 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
687 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
691 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg()
705 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
709 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
714 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
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DThumb1InstrInfo.h43 unsigned DestReg, unsigned SrcReg,
53 unsigned DestReg, int FrameIndex,
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp1267 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg, in forwardCopyWillClobberTuple() argument
1271 return ((DestReg - SrcReg) & 0x1f) < NumRegs; in forwardCopyWillClobberTuple()
1276 unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, in copyPhysRegTuple() argument
1281 uint16_t DestEncoding = TRI->getEncodingValue(DestReg); in copyPhysRegTuple()
1294 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyPhysRegTuple()
1302 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
1304 if (AArch64::GPR32spRegClass.contains(DestReg) && in copyPhysReg()
1308 if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) { in copyPhysReg()
1312 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32, in copyPhysReg()
1326 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg) in copyPhysReg()
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DAArch64A57FPLoadBalancing.cpp590 unsigned DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
593 << TRI->getName(DestReg) << " at " << *MI); in scanInstruction()
595 auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg)); in scanInstruction()
596 ActiveChains[DestReg] = G.get(); in scanInstruction()
603 unsigned DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
608 if (DestReg != AccumReg) in scanInstruction()
623 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); in scanInstruction()
625 if (DestReg != AccumReg) { in scanInstruction()
626 ActiveChains[DestReg] = ActiveChains[AccumReg]; in scanInstruction()
638 << TRI->getName(DestReg) << "\n"); in scanInstruction()
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DAArch64InstrInfo.h104 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
108 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
118 MachineBasicBlock::iterator MBBI, unsigned DestReg,
170 DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp37 unsigned DestReg, unsigned SrcReg, bool KillSrc) const { in copyPhysReg() argument
39 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg()
46 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg) in copyPhysReg()
49 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg) in copyPhysReg()
52 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg) in copyPhysReg()
55 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg) in copyPhysReg()
58 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg) in copyPhysReg()
61 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg) in copyPhysReg()
69 unsigned &DestReg) const { in isMoveInstr()
84 DestReg = dest.getReg(); in isMoveInstr()
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp84 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
89 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
110 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
118 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
120 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
122 else if (Mips::HI32RegClass.contains(DestReg)) in copyPhysReg()
123 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
124 else if (Mips::LO32RegClass.contains(DestReg)) in copyPhysReg()
125 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
126 else if (Mips::HI32DSPRegClass.contains(DestReg)) in copyPhysReg()
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DMipsFastISel.cpp326 unsigned DestReg = createResultReg(RC); in MaterializeFP() local
328 EmitInst(Mips::MTC1, DestReg).addReg(TempReg); in MaterializeFP()
329 return DestReg; in MaterializeFP()
332 unsigned DestReg = createResultReg(RC); in MaterializeFP() local
336 EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in MaterializeFP()
337 return DestReg; in MaterializeFP()
347 unsigned DestReg = createResultReg(RC); in MaterializeGV() local
353 EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress( in MaterializeGV()
355 return DestReg; in MaterializeGV()
DMips16InstrInfo.cpp66 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
70 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
73 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
77 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
81 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
89 if (DestReg) in copyPhysReg()
90 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
115 unsigned DestReg, int FI, const TargetRegisterClass *RC, in loadRegFromStack() argument
125 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset) in loadRegFromStack()
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp283 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
295 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
296 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
298 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
299 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
301 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
303 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
311 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
314 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
338 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]); in copyPhysReg()
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/external/llvm/lib/Target/R600/
DR600MachineScheduler.cpp273 unsigned DestReg = MI->getOperand(0).getReg(); in getAluKind() local
274 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) || in getAluKind()
275 regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass)) in getAluKind()
277 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass)) in getAluKind()
279 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass)) in getAluKind()
281 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass)) in getAluKind()
283 if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass)) in getAluKind()
362 unsigned DestReg = MI->getOperand(DstIndex).getReg(); in AssignSlot() local
369 MO.getReg() == DestReg) in AssignSlot()
375 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass); in AssignSlot()
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/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h240 unsigned DestReg) { in BuildMI() argument
242 .addReg(DestReg, RegState::Define); in BuildMI()
253 unsigned DestReg) { in BuildMI() argument
257 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
264 unsigned DestReg) { in BuildMI() argument
268 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
275 unsigned DestReg) { in BuildMI() argument
278 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
282 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
339 unsigned DestReg) { in BuildMI() argument
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/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp120 unsigned DestReg = MI->getOperand(0).getReg(); in expandRIEPseudo() local
122 bool DestIsHigh = isHighReg(DestReg); in expandRIEPseudo()
128 DestReg, SrcReg, SystemZ::LR, 32, in expandRIEPseudo()
131 MI->getOperand(1).setReg(DestReg); in expandRIEPseudo()
164 DebugLoc DL, unsigned DestReg, in emitGRX32Move() argument
168 bool DestIsHigh = isHighReg(DestReg); in emitGRX32Move()
177 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg) in emitGRX32Move()
182 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) in emitGRX32Move()
183 .addReg(DestReg, RegState::Undef) in emitGRX32Move()
555 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
DSIInstrInfo.cpp39 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); in copyPhysReg()
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) in copyPhysReg()
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.cpp39 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); in copyPhysReg()
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) in copyPhysReg()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp67 unsigned DestReg, int FrameIdx, in loadRegFromStackSlot() argument
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
86 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
93 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
103 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp626 unsigned DestReg, in insertSelect() argument
684 BuildMI(MBB, MI, dl, get(OpCode), DestReg) in insertSelect()
691 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
696 if (PPC::F8RCRegClass.contains(DestReg) && in copyPhysReg()
699 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
704 DestReg = SuperReg; in copyPhysReg()
705 } else if (PPC::VRRCRegClass.contains(DestReg) && in copyPhysReg()
708 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass); in copyPhysReg()
713 DestReg = SuperReg; in copyPhysReg()
715 PPC::VSLRCRegClass.contains(DestReg)) { in copyPhysReg()
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/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp343 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
345 bool GRDest = XCore::GRRegsRegClass.contains(DestReg); in copyPhysReg()
349 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) in copyPhysReg()
356 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); in copyPhysReg()
360 if (DestReg == XCore::SP && GRSrc) { in copyPhysReg()
394 unsigned DestReg, int FrameIndex, in loadRegFromStackSlot() argument
408 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) in loadRegFromStackSlot()

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