| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrAlias.td | 43 // Alias of: memXX($Rs+#XX) = $Rt to memXX($Rs) = $Rt
44 def : InstAlias<"memb($Rs) = $Rt",
45 (S2_storerb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
47 def : InstAlias<"memh($Rs) = $Rt",
48 (S2_storerh_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
50 def : InstAlias<"memh($Rs) = $Rt.h",
51 (S2_storerf_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
53 def : InstAlias<"memw($Rs) = $Rt",
54 (S2_storeri_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
56 def : InstAlias<"memb($Rs) = $Rt.new",
[all …]
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| D | HexagonIsetDx.td | 82 (ins IntRegs:$Rs, u4_0Imm:$u4_0),
83 "memb($Rs + #$u4_0)=#0"> {
84 bits<4> Rs;
88 let Inst{7-4} = Rs;
109 (ins IntRegs:$Rs, u3_1Imm:$u3_1),
110 "$Rd = memuh($Rs + #$u3_1)"> {
112 bits<4> Rs;
117 let Inst{7-4} = Rs;
151 (ins IntRegs:$Rs, u4_0Imm:$u4_0),
152 "$Rd = memub($Rs + #$u4_0)"> {
[all …]
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| D | HexagonInstrInfoVector.td | 138 def: Pat<(v4i8 (HexagonVSPLATB I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
142 def: Pat<(v4i16 (HexagonVSPLATH I32:$Rs)), (S2_vsplatrh I32:$Rs)>;
200 def: Pat<(v2i32 (HexagonVSRAW V2I32:$Rs, u5ImmPred:$u5)),
201 (S2_asr_i_vw V2I32:$Rs, imm:$u5)>;
202 def: Pat<(v4i16 (HexagonVSRAH V4I16:$Rs, u4ImmPred:$u4)),
203 (S2_asr_i_vh V4I16:$Rs, imm:$u4)>;
204 def: Pat<(v2i32 (HexagonVSRLW V2I32:$Rs, u5ImmPred:$u5)),
205 (S2_lsr_i_vw V2I32:$Rs, imm:$u5)>;
206 def: Pat<(v4i16 (HexagonVSRLH V4I16:$Rs, u4ImmPred:$u4)),
207 (S2_lsr_i_vh V4I16:$Rs, imm:$u4)>;
[all …]
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| D | HexagonIntrinsics.td | 21 : Pat <(IntID I32:$Rs),
22 (MI I32:$Rs)>;
25 : Pat <(IntID I64:$Rs),
26 (MI DoubleRegs:$Rs)>;
33 : Pat<(IntID I32:$Rs, ImmPred:$It),
34 (MI I32:$Rs, ImmPred:$It)>;
41 : Pat<(IntID I64:$Rs, imm:$It),
42 (MI DoubleRegs:$Rs, imm:$It)>;
45 : Pat<(IntID I32:$Rs, I64:$Rt),
46 (MI I32:$Rs, DoubleRegs:$Rt)>;
[all …]
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| D | HexagonInstrInfo.td | 30 def LoReg: OutPatFrag<(ops node:$Rs),
31 (EXTRACT_SUBREG (i64 $Rs), subreg_loreg)>;
32 def HiReg: OutPatFrag<(ops node:$Rs),
33 (EXTRACT_SUBREG (i64 $Rs), subreg_hireg)>;
121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
122 "$Rd = "#mnemonic#"($Rs, $Rt)",
128 bits<5> Rs;
136 let Inst{20-16} = !if(OpsRev,Rt,Rs);
137 let Inst{12-8} = !if(OpsRev,Rs,Rt);
144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
[all …]
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| D | HexagonInstrInfoV4.td | 131 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
165 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
166 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
175 bits<5> Rs;
180 let Inst{20-16} = Rs;
194 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
196 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
197 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
199 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
200 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
[all …]
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| D | HexagonInstrInfoV5.td | 32 // Rdd=vmpyb[s]u(Rs,Rt)
37 // Rxx+=vmpyb[s]u(Rs,Rt)
153 (ins IntRegs:$Rs, IntRegs:$Rt),
154 "$Rd = "#mnemonic#"($Rs, $Rt)", [],
158 bits<5> Rs;
165 let Inst{20-16} = Rs;
219 (ins IntRegs:$Rs, IntRegs:$Rt),
220 "$Rd, $Pe = sfrecipa($Rs, $Rt)">,
224 bits<5> Rs;
229 let Inst{20-16} = Rs;
[all …]
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| D | HexagonIntrinsicsV4.td | 33 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
37 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
42 // Rdd=vpmpyh(Rs,Rt)
44 // Rxx[^]=vpmpyh(Rs,Rt)
48 // Rdd=pmpyw(Rs,Rt)
50 // Rxx^=pmpyw(Rs,Rt)
262 Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt, IntRegs:$Ru)),
263 (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs),
307 // Rd=[cround|round](Rs,Rt)[:sat]
308 // Rd=[cround|round](Rs,#u5)[:sat]
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| D | HexagonInstrInfoV3.td | 103 (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
104 [(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))),
111 : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
113 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
115 bits<5> Rs;
122 let Inst{20-16} = !if(isMax, Rt, Rs);
123 let Inst{12-8} = !if(isMax, Rs, Rt);
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| D | HexagonSplitDouble.cpp | 82 void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
135 const USet &Rs = I.second; in isInduction() local
136 if (Rs.find(Reg) != Rs.end()) in isInduction()
444 USet &Rs) { in collectIndRegsForLoop() argument
527 Rs.insert(DP.begin(), End); in collectIndRegsForLoop()
528 Rs.insert(CmpR1); in collectIndRegsForLoop()
529 Rs.insert(CmpR2); in collectIndRegsForLoop()
533 dump_partition(dbgs(), Rs, *TRI); in collectIndRegsForLoop()
550 USet Rs; in collectIndRegs() local
553 Rs.clear(); in collectIndRegs()
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | alu64.ll | 5 define i32 @test00(i64 %Rs, i64 %Rt) #0 {
7 %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt)
13 define i32 @test01(i64 %Rs, i64 %Rt) #0 {
15 %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt)
21 define i32 @test02(i64 %Rs, i64 %Rt) #0 {
23 %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt)
29 define i32 @test10(i32 %Rs, i32 %Rt) #0 {
31 %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt)
37 define i32 @test11(i32 %Rs, i32 %Rt) #0 {
39 %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt)
[all …]
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| D | usr-ovf-dep.ll | 15 define i32 @foo(i32 %Rs, i32 %Rt, i32 %Ru) #0 {
17 %0 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %Rs, i32 %Ru)
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 207 MCOperand Rs, Rt; in getCompoundInsn() local
229 Rs = L.getOperand(1); in getCompoundInsn()
235 CompoundInsn->addOperand(Rs); in getCompoundInsn()
242 Rs = L.getOperand(1); in getCompoundInsn()
248 CompoundInsn->addOperand(Rs); in getCompoundInsn()
255 Rs = L.getOperand(1); in getCompoundInsn()
261 CompoundInsn->addOperand(Rs); in getCompoundInsn()
268 Rs = L.getOperand(1); in getCompoundInsn()
274 CompoundInsn->addOperand(Rs); in getCompoundInsn()
289 Rs = L.getOperand(1); in getCompoundInsn()
[all …]
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| /external/icu/icu4c/source/data/curr/ |
| D | root.txt | 148 LKR{"Rs"}
155 MUR{"Rs"}
162 NPR{"Rs"}
165 PKR{"Rs"}
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| D | ur.txt | 460 "Rs",
720 LKR{"Rs"}
725 MUR{"Rs"}
732 NPR{"Rs"}
735 PKR{"Rs"}
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| D | km.txt | 695 LKR{"Rs"}
700 MUR{"Rs"}
706 NPR{"Rs"}
709 PKR{"Rs"}
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| D | mzn.txt | 642 LKR{"Rs"}
647 MUR{"Rs"}
654 NPR{"Rs"}
656 PKR{"Rs"}
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| D | ta_LK.txt | 12 "Rs.",
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| D | fr_MU.txt | 12 "Rs",
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| D | en_PK.txt | 13 "Rs",
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| D | en_MU.txt | 13 "Rs",
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 564 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
569 if (Rs >= Rt) { in DecodeAddiGroupBranch()
572 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
580 Rs))); in DecodeAddiGroupBranch()
603 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch() local
608 if (Rs >= Rt) { in DecodeDaddiGroupBranch()
611 } else if (Rs != 0 && Rs < Rt) { in DecodeDaddiGroupBranch()
619 Rs))); in DecodeDaddiGroupBranch()
643 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch() local
650 else if (Rs == 0) in DecodeBlezlGroupBranch()
[all …]
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1843 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1851 TmpInst.addOperand(Rs); in processInstruction()
1862 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1870 TmpInst.addOperand(Rs); in processInstruction()
1881 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1889 TmpInst.addOperand(Rs); in processInstruction()
1903 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1924 TmpInst.addOperand(Rs); in processInstruction()
1940 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1942 TmpInst.addOperand(Rs); in processInstruction()
[all …]
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| /external/mesa3d/src/mesa/swrast/ |
| D | s_blend.c | 483 const GLfloat Rs = rgba[i][RCOMP]; in blend_general_float() local
557 sR = Rs; in blend_general_float()
562 sR = 1.0F - Rs; in blend_general_float()
635 dR = Rs; in blend_general_float()
640 dR = 1.0F - Rs; in blend_general_float()
743 r = Rs * sR + Rd * dR; in blend_general_float()
749 r = Rs * sR - Rd * dR; in blend_general_float()
755 r = Rd * dR - Rs * sR; in blend_general_float()
761 r = MIN2( Rd, Rs ); in blend_general_float()
766 r = MAX2( Rd, Rs ); in blend_general_float()
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| /external/eigen/Eigen/src/UmfPackSupport/ |
| D | UmfPackSupport.h | 84 … int P[], int Q[], double Dx[], int *do_recip, double Rs[], void *Numeric) in umfpack_get_numeric() argument
86 return umfpack_di_get_numeric(Lp,Lj,Lx,Up,Ui,Ux,P,Q,Dx,do_recip,Rs,Numeric); in umfpack_get_numeric()
90 … int P[], int Q[], std::complex<double> Dx[], int *do_recip, double Rs[], void *Numeric) in umfpack_get_numeric() argument
96 Dx?&dx0_real:0,0,do_recip,Rs,Numeric); in umfpack_get_numeric()
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