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Searched refs:SRL (Results 1 – 25 of 91) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp136 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
139 { ISD::SRL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
152 { ISD::SRL, MVT::v4i32, 1 }, in getArithmeticInstrCost()
155 { ISD::SRL, MVT::v8i32, 1 }, in getArithmeticInstrCost()
158 { ISD::SRL, MVT::v2i64, 1 }, in getArithmeticInstrCost()
160 { ISD::SRL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
179 { ISD::SRL, MVT::v16i8, 2 }, in getArithmeticInstrCost()
182 { ISD::SRL, MVT::v8i16, 2 }, in getArithmeticInstrCost()
185 { ISD::SRL, MVT::v4i32, 2 }, in getArithmeticInstrCost()
188 { ISD::SRL, MVT::v2i64, 2 }, in getArithmeticInstrCost()
[all …]
/external/llvm/test/CodeGen/Mips/
Dfcopysign-f32-f64.ll39 ; 64-DAG: srl $[[SRL:[0-9]+]], ${{[0-9]+}}, 31
40 ; 64-DAG: sll $[[SLL:[0-9]+]], $[[SRL]], 0
/external/llvm/test/CodeGen/SystemZ/
Dshift-09.ll25 ; Check that we use SRLK over SRL where useful.
35 ; Check that we use SRL over SRLK where possible.
Dshift-02.ll5 ; Check the low end of the SRL range.
14 ; Check the high end of the defined SRL range.
Dshift-10.ll69 ; Test that SRA gets replaced with SRL if the sign bit is the only one
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp630 if (InOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
638 Opc = ISD::SRL; in SimplifyDemandedBits()
678 InnerOp.getOpcode() == ISD::SRL && in SimplifyDemandedBits()
705 case ISD::SRL: in SimplifyDemandedBits()
730 unsigned Opc = ISD::SRL; in SimplifyDemandedBits()
763 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), in SimplifyDemandedBits()
803 TLO.DAG.getNode(ISD::SRL, dl, VT, Op.getOperand(0), in SimplifyDemandedBits()
813 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, in SimplifyDemandedBits()
1011 case ISD::SRL: in SimplifyDemandedBits()
1015 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) in SimplifyDemandedBits()
[all …]
DLegalizeIntegerTypes.cpp87 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; in PromoteIntegerResult()
315 ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
328 ISD::SRL, dl, NVT, DAG.getNode(ISD::BITREVERSE, dl, NVT, Op), in PromoteIntRes_BITREVERSE()
684 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS); in PromoteIntRes_SRL()
783 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, in PromoteIntRes_XMULO()
915 case ISD::SRL: in PromoteIntegerOperand()
1385 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; in ExpandIntegerResult()
1456 DAG.getNode(ISD::SRL, DL, NVT, InL, in ExpandShiftByConstant()
1462 if (N->getOpcode() == ISD::SRL) { in ExpandShiftByConstant()
1466 Lo = DAG.getNode(ISD::SRL, DL, in ExpandShiftByConstant()
[all …]
DLegalizeVectorOps.cpp280 case ISD::SRL: in LegalizeOp()
577 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt); in ExpandLoad()
917 !TLI.isOperationLegalOrCustom(ISD::SRL, VT) || in ExpandBITREVERSE()
979 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) in ExpandUINT_TO_FLOAT()
999 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord); in ExpandUINT_TO_FLOAT()
DLegalizeDAG.cpp416 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
828 ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
840 ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
1358 case ISD::SRL: in LegalizeOp()
2602 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, in ExpandLegalINT_TO_FP()
2623 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); in ExpandLegalINT_TO_FP()
2659 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, in ExpandLegalINT_TO_FP()
2825 DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT)); in ExpandBITREVERSE()
2845 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in ExpandBSWAP()
2850 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT)); in ExpandBSWAP()
[all …]
DDAGCombiner.cpp1116 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1387 case ISD::SRL: return visitSRL(N); in visit()
1486 case ISD::SRL: in combine()
2281 SDValue SRL = in visitSDIV() local
2282 DAG.getNode(ISD::SRL, DL, VT, SGN, in visitSDIV()
2285 SDValue ADD = DAG.getNode(ISD::ADD, DL, VT, N0, SRL); in visitSDIV()
2286 AddToWorklist(SRL.getNode()); in visitSDIV()
2347 return DAG.getNode(ISD::SRL, DL, VT, N0, in visitUDIV()
2362 return DAG.getNode(ISD::SRL, DL, VT, N0, Add); in visitUDIV()
2505 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
[all …]
/external/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h27 case ISD::SRL: return ARM_AM::lsr; in getShiftOpcForNode()
/external/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.cpp179 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM, in addIPMSequence() local
181 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL, in addIPMSequence()
DSystemZInstrInfo.cpp460 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI); in removeIPMBasedCompare() local
461 if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC)) in removeIPMBasedCompare()
464 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI); in removeIPMBasedCompare()
482 eraseIfDead(SRL, MRI); in removeIPMBasedCompare()
/external/pcre/dist/sljit/
DsljitNativeSPARC_32.c71 …return push_inst(compiler, (op == SLJIT_MOV_SH ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)); in emit_single_op()
130 FAIL_IF(push_inst(compiler, SRL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()
DsljitNativeMIPS_32.c135 FAIL_IF(push_inst(compiler, SRL | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_FLAG)); in emit_single_op()
271 …return push_inst(compiler, SRL | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG… in emit_single_op()
332 EMIT_SHIFT(SRL, SRLV); in emit_single_op()
DsljitNativeMIPS_64.c227 …FAIL_IF(push_inst(compiler, SELECT_OP(DSRL32, SRL) | T(src2) | DA(EQUAL_FLAG) | SH_IMM(31), EQUAL_… in emit_single_op()
363 …return push_inst(compiler, SELECT_OP(DSRL32, SRL) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM… in emit_single_op()
427 EMIT_SHIFT(DSRL, DSRL32, SRL, DSRLV, SRLV); in emit_single_op()
/external/valgrind/none/tests/mips64/
Dshift_instructions.c10 SRA, SRAV, SRL, SRLV enumerator
189 case SRL: in main()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp93 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
96 setOperationAction(ISD::SRL, MVT::i16, Custom); in MSP430TargetLowering()
187 case ISD::SRL: in LowerOperation()
753 case ISD::SRL: in LowerShifts()
754 return DAG.getNode(MSP430ISD::SRL, dl, in LowerShifts()
765 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
1154 case MSP430ISD::SRL: return "MSP430ISD::SRL"; in getTargetNodeName()
DMSP430ISelLowering.h65 SHL, SRA, SRL enumerator
/external/llvm/test/CodeGen/PowerPC/
Dload-shift-combine.ll5 ; load. Later the pre-increment load is combined with a subsequent SRL to
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h336 SHL, SRA, SRL, ROTL, ROTR, enumerator
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1007 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift); in LowerSHLParts()
1008 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One); in LowerSHLParts()
1048 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); in LowerSRXParts()
1049 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift); in LowerSRXParts()
1052 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); in LowerSRXParts()
1281 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
1338 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, VT, Ptr, in LowerSTORE()
1364 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), in LowerSTORE()
1488 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1534 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp495 } else if (Opcode == ISD::SRL) { in isRotateAndMask()
542 Op0.getOperand(0).getOpcode() == ISD::SRL) { in SelectBitfieldInsert()
544 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
550 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { in SelectBitfieldInsert()
552 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
563 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && in SelectBitfieldInsert()
577 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask && in SelectBitfieldInsert()
954 case ISD::SRL: in getValueBits()
1975 case ISD::SRL: in SelectBitPermutation()
2614 if (Val.getOpcode() == ISD::SRL && in Select()
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/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp699 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) in performANDCombine()
1946 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFCOPYSIGN32()
1947 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); in lowerFCOPYSIGN32()
1996 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); in lowerFCOPYSIGN64()
1997 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, in lowerFCOPYSIGN64()
2107 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, in lowerShiftLeftParts()
2109 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); in lowerShiftLeftParts()
2148 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in lowerShiftRightParts()
2150 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, in lowerShiftRightParts()
2241 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); in lowerLOAD() local
[all …]
/external/v8/src/mips/
Dconstants-mips.h413 SRL = ((0U << 3) + 2), enumerator
928 FunctionFieldToBitNumber(SRL) | FunctionFieldToBitNumber(SRA) |

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