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Searched refs:vassert (Results 1 – 25 of 45) sorted by relevance

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/external/valgrind/VEX/priv/
Dmain_main.c91 #define X86ST(f) vassert(0)
99 #define AMD64ST(f) vassert(0)
107 #define PPC32ST(f) vassert(0)
115 #define PPC64ST(f) vassert(0)
123 #define S390ST(f) vassert(0)
131 #define ARMST(f) vassert(0)
139 #define ARM64ST(f) vassert(0)
147 #define MIPS32ST(f) vassert(0)
155 #define MIPS64ST(f) vassert(0)
212 vassert(!vex_initdone); in LibVEX_Init()
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Dhost_generic_reg_alloc2.c175 vassert(search_from_instr >= 0); in findMostDistantlyMentionedVReg()
179 vassert(state[k].disp == Bound); in findMostDistantlyMentionedVReg()
199 vassert(0 == ((UShort)vreg->spill_offset % 16)); break; in sanity_check_spill_offset()
201 vassert(0 == ((UShort)vreg->spill_offset % 8)); break; in sanity_check_spill_offset()
214 vassert(used == *size); in ensureRRLRspace_SLOW()
242 vassert(size >= 0); in sortRRLRarray()
450 vassert(0 == (guest_sizeB % LibVEX_GUEST_STATE_ALIGN)); in doRegisterAllocation()
451 vassert(0 == (LibVEX_N_SPILL_BYTES % LibVEX_GUEST_STATE_ALIGN)); in doRegisterAllocation()
452 vassert(0 == (N_SPILL64S % 2)); in doRegisterAllocation()
457 vassert(instrs_in->arr_used <= 15000); in doRegisterAllocation()
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Dmain_util.c80 vassert(temporary_first == &temporary[0]); in vexAllocSanityCheck()
81 vassert(temporary_last == &temporary[N_TEMPORARY_BYTES-1]); in vexAllocSanityCheck()
82 vassert(permanent_first == &permanent[0]); in vexAllocSanityCheck()
83 vassert(permanent_last == &permanent[N_PERMANENT_BYTES-1]); in vexAllocSanityCheck()
84 vassert(temporary_first <= temporary_curr); in vexAllocSanityCheck()
85 vassert(temporary_curr <= temporary_last); in vexAllocSanityCheck()
86 vassert(permanent_first <= permanent_curr); in vexAllocSanityCheck()
87 vassert(permanent_curr <= permanent_last); in vexAllocSanityCheck()
88 vassert(private_LibVEX_alloc_first <= private_LibVEX_alloc_curr); in vexAllocSanityCheck()
89 vassert(private_LibVEX_alloc_curr <= private_LibVEX_alloc_last); in vexAllocSanityCheck()
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Dhost_generic_regs.c103 vassert(univ->size > 0); in RRegUniverse__check_is_sane()
104 vassert(univ->size <= N_RREGUNIVERSE_REGS); in RRegUniverse__check_is_sane()
105 vassert(univ->allocable <= univ->size); in RRegUniverse__check_is_sane()
108 vassert(!hregIsInvalid(reg)); in RRegUniverse__check_is_sane()
109 vassert(!hregIsVirtual(reg)); in RRegUniverse__check_is_sane()
110 vassert(hregIndex(reg) == i); in RRegUniverse__check_is_sane()
114 vassert(hregIsInvalid(reg)); in RRegUniverse__check_is_sane()
127 vassert(N_RREGUNIVERSE_REGS == 64); in ppHRegUsage()
177 vassert(tab->n_vRegs < N_HREGUSAGE_VREGS); in addHRegUse()
202 vassert(ix < N_RREGUNIVERSE_REGS); in addHRegUse()
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Dhost_arm64_defs.c156 vassert(r >= 0 && r < 31); in ppHRegARM64()
161 vassert(r >= 0 && r < 32); in ppHRegARM64()
166 vassert(r >= 0 && r < 32); in ppHRegARM64()
217 vassert(-256 <= simm9 && simm9 <= 255); in ARM64AMode_RI9()
227 vassert(uimm12 >= 0 && uimm12 <= 4095); in ARM64AMode_RI12()
230 default: vassert(0); in ARM64AMode_RI12()
264 vassert(0); in ppARM64AMode()
310 vassert(imm12 < 4096); in ARM64RIA_I12()
311 vassert(shift == 0 || shift == 12); in ARM64RIA_I12()
331 vassert(0); in ppARM64RIA()
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Dhost_ppc_defs.c170 vassert(r >= 0 && r < 32); in ppHRegPPC()
175 vassert(r >= 0 && r < 32); in ppHRegPPC()
180 vassert(r >= 0 && r < 32); in ppHRegPPC()
185 vassert(r >= 0 && r < 32); in ppHRegPPC()
222 vassert(flag == Pcf_NONE); in mk_PPCCondCode()
224 vassert(flag != Pcf_NONE); in mk_PPCCondCode()
232 vassert(ct != Pct_ALWAYS); in invertCondTest()
241 vassert(idx >= -0x8000 && idx < 0x8000); in PPCAMode_IR()
324 vassert(imm16 != 0x8000); in PPCRH_Imm()
325 vassert(syned == True || syned == False); in PPCRH_Imm()
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Dhost_arm64_isel.c117 vassert(tmp >= 0); in lookupIRTemp()
118 vassert(tmp < env->n_vregmap); in lookupIRTemp()
125 vassert(tmp >= 0); in lookupIRTempPair()
126 vassert(tmp < env->n_vregmap); in lookupIRTempPair()
127 vassert(! hregIsInvalid(env->vregmapHI[tmp])); in lookupIRTempPair()
234 vassert(off < (8 << 12)); /* otherwise it's unrepresentable */ in mk_baseblock_64bit_access_amode()
235 vassert((off & 7) == 0); /* ditto */ in mk_baseblock_64bit_access_amode()
242 vassert(off < (4 << 12)); /* otherwise it's unrepresentable */ in mk_baseblock_32bit_access_amode()
243 vassert((off & 3) == 0); /* ditto */ in mk_baseblock_32bit_access_amode()
250 vassert(off < (2 << 12)); /* otherwise it's unrepresentable */ in mk_baseblock_16bit_access_amode()
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Dhost_mips_defs.c159 vassert(hregClass(reg) == HRcInt32 || hregClass(reg) == HRcInt64 || in ppHRegMIPS()
166 vassert(r >= 0 && r < 32); in ppHRegMIPS()
171 vassert (r >= 0 && r < 32); in ppHRegMIPS()
176 vassert(r >= 0 && r < 32); in ppHRegMIPS()
181 vassert(r >= 0 && r < 32); in ppHRegMIPS()
589 vassert(imm16 != 0x8000); in MIPSRH_Imm()
590 vassert(syned == True || syned == False); in MIPSRH_Imm()
697 vassert(immR == False); /*there's no nor with an immediate operand!? */ in showMIPSAluOp()
880 vassert(0 == (argiregs & ~mask)); in MIPSInstr_Call()
881 vassert(is_sane_RetLoc(rloc)); in MIPSInstr_Call()
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Dguest_generic_bb_to_IR.c225 vassert(sizeof(HWord) == sizeof(void*)); in bb_to_IR()
226 vassert(vex_control.guest_max_insns >= 1); in bb_to_IR()
227 vassert(vex_control.guest_max_insns <= 100); in bb_to_IR()
228 vassert(vex_control.guest_chase_thresh >= 0); in bb_to_IR()
229 vassert(vex_control.guest_chase_thresh < vex_control.guest_max_insns); in bb_to_IR()
230 vassert(guest_word_type == Ity_I32 || guest_word_type == Ity_I64); in bb_to_IR()
233 vassert(szB_GUEST_IP == 4); in bb_to_IR()
234 vassert((offB_GUEST_IP % 4) == 0); in bb_to_IR()
236 vassert(szB_GUEST_IP == 8); in bb_to_IR()
237 vassert((offB_GUEST_IP % 8) == 0); in bb_to_IR()
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Dhost_s390_defs.c69 vassert(ix >= 0); in s390_hreg_gpr()
77 vassert(ix >= 0); in s390_hreg_fpr()
119 vassert(r < 16); in s390_hreg_as_string()
165 vassert(fits_unsigned_12bit(d)); in s390_amode_b12()
182 vassert(fits_signed_20bit(d)); in s390_amode_b20()
199 vassert(fits_unsigned_12bit(d)); in s390_amode_bx12()
200 vassert(hregNumber(b) != 0); in s390_amode_bx12()
201 vassert(hregNumber(x) != 0); in s390_amode_bx12()
218 vassert(fits_signed_20bit(d)); in s390_amode_bx20()
219 vassert(hregNumber(b) != 0); in s390_amode_bx20()
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Dguest_arm64_toIR.c150 vassert(n > 1 && n < 64); in sx_to_64()
261 vassert(i < 65536); in mkU16()
267 vassert(i < 256); in mkU8()
358 vassert(isPlausibleIRType(ty)); in newTemp()
372 vassert(t1 && *t1 == IRTemp_INVALID); in newTempsV128_2()
373 vassert(t2 && *t2 == IRTemp_INVALID); in newTempsV128_2()
381 vassert(t1 && *t1 == IRTemp_INVALID); in newTempsV128_3()
382 vassert(t2 && *t2 == IRTemp_INVALID); in newTempsV128_3()
383 vassert(t3 && *t3 == IRTemp_INVALID); in newTempsV128_3()
392 vassert(t1 && *t1 == IRTemp_INVALID); in newTempsV128_4()
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Dhost_amd64_defs.c119 vassert(r >= 0 && r < 16); in ppHRegAMD64()
124 vassert(r >= 0 && r < 16); in ppHRegAMD64()
148 vassert(r >= 0 && r < 16); in ppHRegAMD64_lo32()
200 vassert(shift >= 0 && shift <= 3); in AMD64AMode_IRRS()
610 vassert(op != Aalu_MUL); in AMD64Instr_Alu64M()
651 default: vassert(0); in AMD64Instr_Alu32R()
668 vassert(sz == 4 || sz == 8); in AMD64Instr_Div()
685 vassert(regparms >= 0 && regparms <= 6); in AMD64Instr_Call()
686 vassert(is_sane_RetLoc(rloc)); in AMD64Instr_Call()
726 vassert(cond != Acc_ALWAYS); in AMD64Instr_CMov64()
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Dir_opt.c254 vassert(h->used < h->size); in addToHHW()
486 vassert(d2->mAddr == NULL); in flatten_Stmt()
560 vassert((*minoff & ~0xFFFF) == 0); in getArrayBounds()
561 vassert((*maxoff & ~0xFFFF) == 0); in getArrayBounds()
562 vassert(*minoff <= *maxoff); in getArrayBounds()
572 vassert((minoff & ~0xFFFF) == 0); in mk_key_GetPut()
573 vassert((maxoff & ~0xFFFF) == 0); in mk_key_GetPut()
581 vassert((minoff & ~0xFFFF) == 0); in mk_key_GetIPutI()
582 vassert((maxoff & ~0xFFFF) == 0); in mk_key_GetIPutI()
594 vassert(k_lo <= k_hi); in invalidateOverlaps()
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Dhost_mips_isel.c132 vassert(tmp < env->n_vregmap); in lookupIRTemp()
138 vassert(tmp < env->n_vregmap); in lookupIRTemp64()
139 vassert(! hregIsInvalid(env->vregmapHI[tmp])); in lookupIRTemp64()
147 vassert(env->mode64); in lookupIRTempPair()
148 vassert(tmp < env->n_vregmap); in lookupIRTempPair()
149 vassert(! hregIsInvalid(env->vregmapHI[tmp])); in lookupIRTempPair()
190 vassert(n < 256 && (n % 8) == 0); in add_to_sp()
202 vassert(n < 256 && (n % 8) == 0); in sub_from_sp()
322 vassert(hregClass(r_dst) == hregClass(r_src)); in mk_iMOVds_RR()
323 vassert(hregClass(r_src) == HRcInt32 || hregClass(r_src) == HRcInt64); in mk_iMOVds_RR()
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Dhost_arm_isel.c131 vassert(tmp >= 0); in lookupIRTemp()
132 vassert(tmp < env->n_vregmap); in lookupIRTemp()
138 vassert(tmp >= 0); in lookupIRTemp64()
139 vassert(tmp < env->n_vregmap); in lookupIRTemp64()
140 vassert(! hregIsInvalid(env->vregmapHI[tmp])); in lookupIRTemp64()
257 vassert(sh >= 0 && sh < 32); in ROR32()
277 vassert(i == 16); in fitsIn8x4()
284 vassert(hregClass(src) == HRcInt32); in mk_iMOVds_RR()
285 vassert(hregClass(dst) == HRcInt32); in mk_iMOVds_RR()
439 vassert(n_real_args <= 12); in doHelperCallWithArgsOnStack()
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Dguest_arm_helpers.c99 vassert( ((UInt)(_cc_op)) < ARMG_CC_OP_NUMBER); \
146 vassert((oldC & ~1) == 0); in armg_calculate_flag_n()
156 vassert((oldC & ~1) == 0); in armg_calculate_flag_n()
226 vassert((oldC & ~1) == 0); in armg_calculate_flag_z()
236 vassert((oldC & ~1) == 0); in armg_calculate_flag_z()
306 vassert((oldC & ~1) == 0); in armg_calculate_flag_c()
316 vassert((oldC & ~1) == 0); in armg_calculate_flag_c()
323 vassert((shco & ~1) == 0); in armg_calculate_flag_c()
330 vassert((cc_dep3 & ~3) == 0); in armg_calculate_flag_c()
337 vassert((cc_dep3 & ~3) == 0); in armg_calculate_flag_c()
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Dhost_generic_regs.h136 vassert(ix <= 0xFFFFF); in mkHReg()
137 vassert(enc <= 0x7F); in mkHReg()
138 vassert(((UInt)rc) <= 0xF); in mkHReg()
139 vassert(((UInt)virtual) <= 1); in mkHReg()
140 if (virtual) vassert(enc == 0); in mkHReg()
152 vassert(rc >= HRcInt32 && rc <= HRcVec128); in hregClass()
412 vassert(pri >= RLPri_INVALID && pri <= RLPri_2Int); in mk_RetLoc_simple()
417 vassert(pri >= RLPri_V128SpRel && pri <= RLPri_V256SpRel); in mk_RetLoc_spRel()
Dhost_x86_defs.c112 vassert(r >= 0 && r < 8); in ppHRegX86()
117 vassert(r >= 0 && r < 6); in ppHRegX86()
122 vassert(r >= 0 && r < 8); in ppHRegX86()
174 vassert(shift >= 0 && shift <= 3); in X86AMode_IRRS()
578 vassert(op != Xalu_MUL); in X86Instr_Alu32M()
631 vassert(op == Xsh_SHL || op == Xsh_SHR); in X86Instr_Sh3232()
648 vassert(regparms >= 0 && regparms <= 3); in X86Instr_Call()
649 vassert(is_sane_RetLoc(rloc)); in X86Instr_Call()
687 vassert(cond != Xcc_ALWAYS); in X86Instr_CMov32()
698 vassert(szSmall == 1 || szSmall == 2); in X86Instr_LoadEX()
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Dhost_x86_isel.c195 vassert(tmp >= 0); in lookupIRTemp()
196 vassert(tmp < env->n_vregmap); in lookupIRTemp()
202 vassert(tmp >= 0); in lookupIRTemp64()
203 vassert(tmp < env->n_vregmap); in lookupIRTemp64()
204 vassert(! hregIsInvalid(env->vregmapHI[tmp])); in lookupIRTemp64()
291 vassert(hregClass(src) == HRcInt32); in mk_iMOVsd_RR()
292 vassert(hregClass(dst) == HRcInt32); in mk_iMOVsd_RR()
301 vassert(hregClass(src) == HRcVec128); in mk_vMOVsd_RR()
302 vassert(hregClass(dst) == HRcVec128); in mk_vMOVsd_RR()
310 vassert(n > 0 && n < 256 && (n%4) == 0); in add_to_esp()
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Dhost_ppc_isel.c304 vassert(tmp >= 0); in lookupIRTemp()
305 vassert(tmp < env->n_vregmap); in lookupIRTemp()
312 vassert(tmp >= 0); in lookupIRTempPair()
313 vassert(tmp < env->n_vregmap); in lookupIRTempPair()
314 vassert(! hregIsInvalid(env->vregmapMedLo[tmp])); in lookupIRTempPair()
323 vassert(!env->mode64); in lookupIRTempQuad()
324 vassert(tmp >= 0); in lookupIRTempQuad()
325 vassert(tmp < env->n_vregmap); in lookupIRTempQuad()
326 vassert(! hregIsInvalid(env->vregmapMedLo[tmp])); in lookupIRTempQuad()
519 vassert(hregClass(r_dst) == hregClass(r_src)); in mk_iMOVds_RR()
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Dhost_arm_defs.c154 vassert(r >= 0 && r < 16); in ppHRegARM()
159 vassert(r >= 0 && r < 32); in ppHRegARM()
164 vassert(r >= 0 && r < 32); in ppHRegARM()
169 vassert(r >= 0 && r < 16); in ppHRegARM()
210 vassert(-4095 <= simm13 && simm13 <= 4095); in ARMAMode1_RI()
219 vassert(0 <= shift && shift <= 3); in ARMAMode1_RRS()
238 vassert(0); in ppARMAMode1()
278 vassert(-255 <= simm9 && simm9 <= 255); in ARMAMode2_RI()
304 vassert(0); in ppARMAMode2()
341 vassert(simm11 >= -1020 && simm11 <= 1020); in mkARMAModeV()
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Dguest_arm_toIR.c180 do { vassert(__curr_is_Thumb); } while (0)
183 do { vassert(! __curr_is_Thumb); } while (0)
214 vassert(sh >= 0 && sh < 32); in ROR32()
297 vassert(i < 256); in mkU8()
372 vassert(0); in loadGuardedLE()
374 vassert(loaded != NULL); in loadGuardedLE()
388 vassert(isPlausibleIRType(ty)); in newTemp()
402 vassert(rot >= 0 && rot < 32); in genROR32()
524 default: vassert(0); in integerGuestRegOffset()
531 vassert(iregNo < 16); in llGetIReg()
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Dhost_amd64_isel.c170 vassert(tmp >= 0); in lookupIRTemp()
171 vassert(tmp < env->n_vregmap); in lookupIRTemp()
178 vassert(tmp >= 0); in lookupIRTempPair()
179 vassert(tmp < env->n_vregmap); in lookupIRTempPair()
180 vassert(! hregIsInvalid(env->vregmapHI[tmp])); in lookupIRTempPair()
312 vassert(hregClass(src) == HRcInt64); in mk_iMOVsd_RR()
313 vassert(hregClass(dst) == HRcInt64); in mk_iMOVsd_RR()
321 vassert(hregClass(src) == HRcVec128); in mk_vMOVsd_RR()
322 vassert(hregClass(dst) == HRcVec128); in mk_vMOVsd_RR()
330 vassert(n > 0 && n < 256 && (n%8) == 0); in add_to_rsp()
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Dir_inject.c88 vassert(type == Ity_I1 || sizeofIRType(type) <= 16); in load()
163 vassert(type == Ity_I1 || sizeofIRType(type) <= 16); in store()
219 vassert(iricb.immediate_index == 0 || iricb.immediate_index == 2); in vex_inject_ir()
222 vassert((iricb.t_opnd2 == Ity_I8) || (iricb.t_opnd2 == Ity_I16) in vex_inject_ir()
252 vassert(iricb.immediate_index == 0 || iricb.immediate_index == 3); in vex_inject_ir()
255 vassert((iricb.t_opnd3 == Ity_I8) || (iricb.t_opnd3 == Ity_I16) in vex_inject_ir()
275 vassert(rounding_mode == NULL); in vex_inject_ir()
285 vassert(iricb.immediate_index == 0 || iricb.immediate_index == 4); in vex_inject_ir()
288 vassert((iricb.t_opnd3 == Ity_I8) || (iricb.t_opnd3 == Ity_I16) in vex_inject_ir()
Dguest_arm64_helpers.c101 vassert( ((UInt)(_cc_op)) < ARM64G_CC_OP_NUMBER); \
102 vassert( ((UInt)(_cond)) < 16); \
161 vassert((oldC & ~1) == 0); in arm64g_calculate_flag_n()
171 vassert((oldC & ~1) == 0); in arm64g_calculate_flag_n()
181 vassert((oldC & ~1) == 0); in arm64g_calculate_flag_n()
191 vassert((oldC & ~1) == 0); in arm64g_calculate_flag_n()
279 vassert((oldC & ~1) == 0); in arm64g_calculate_flag_z()
289 vassert((oldC & ~1) == 0); in arm64g_calculate_flag_z()
299 vassert((oldC & ~1) == 0); in arm64g_calculate_flag_z()
309 vassert((oldC & ~1) == 0); in arm64g_calculate_flag_z()
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