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Searched refs:readw (Results 1 – 25 of 166) sorted by relevance

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/drivers/net/tokenring/
Dlanstreamer.c453 writew(readw(streamer_mmio + BCTL) | BCTL_SOFTRESET, streamer_mmio + BCTL); in streamer_reset()
458 writew(readw(streamer_mmio + BCTL) & ~BCTL_SOFTRESET, in streamer_reset()
462 printk("BCTL: %x\n", readw(streamer_mmio + BCTL)); in streamer_reset()
463 printk("GPR: %x\n", readw(streamer_mmio + GPR)); in streamer_reset()
464 printk("SISRMASK: %x\n", readw(streamer_mmio + SISR_MASK)); in streamer_reset()
466 writew(readw(streamer_mmio + BCTL) | (BCTL_RX_FIFO_8 | BCTL_TX_FIFO_8), streamer_mmio + BCTL ); in streamer_reset()
469 writew(readw(streamer_mmio + GPR) | GPR_AUTOSENSE, in streamer_reset()
506 printk("GPR = %x\n", readw(streamer_mmio + GPR)); in streamer_reset()
511 while (!((readw(streamer_mmio + SISR)) & SISR_SRB_REPLY)) { in streamer_reset()
523 misr = readw(streamer_mmio + MISR_RUM); in streamer_reset()
[all …]
Dolympic.c324 printk("GPR: %x\n",readw(olympic_mmio+GPR)); in olympic_init()
334 writew(readw(olympic_mmio+GPR)|GPR_AUTOSENSE,olympic_mmio+GPR); in olympic_init()
347 writew(readw(olympic_mmio+GPR)|GPR_NEPTUNE_BF,olympic_mmio+GPR); in olympic_init()
350 printk("GPR = %x\n",readw(olympic_mmio + GPR) ) ; in olympic_init()
382 writel(readw(olympic_mmio+LAPWWO),olympic_mmio+LAPA); in olympic_init()
388 init_srb=olympic_priv->olympic_lap + ((readw(olympic_mmio+LAPWWO)) & (~0xf800)); in olympic_init()
399 if(readw(init_srb+6)) { in olympic_init()
400 printk(KERN_INFO "tokenring card initialization failed. errorcode : %x\n",readw(init_srb+6)); in olympic_init()
412 uaa_addr=swab16(readw(init_srb+8)); in olympic_init()
427 olympic_priv->olympic_addr_table_addr = swab16(readw(init_srb + 12)); in olympic_init()
[all …]
D3c359.c221 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; in xl_ee_read()
229 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; in xl_ee_read()
237 return readw(xl_mmio + MMIO_MACDATA) ; in xl_ee_read()
253 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; in xl_ee_write()
261 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; in xl_ee_write()
273 while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ; in xl_ee_write()
409 while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { in xl_hw_reset()
435 printk(KERN_INFO "Read from PMBAR = %04x \n", readw(xl_mmio + MMIO_MACDATA)) ; in xl_hw_reset()
438 if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) { in xl_hw_reset()
443 result_16 = readw(xl_mmio + MMIO_MACDATA) ; in xl_hw_reset()
[all …]
Dibmtr.c277 intf_tbl=ntohs(readw(ram_mapped+ACA_OFFSET+ACA_RW+WRBR_EVEN)); in find_turbo_adapters()
288 turbo_io[index]=ntohs(readw(ram_mapped+intf_tbl+4)); in find_turbo_adapters()
948 ntohs(readw(ti->init_srb + DHB_LENGTH_OFST)), in tok_open_adapter()
949 ntohs(readw(ti->init_srb + NUM_RCV_BUF_OFST)), in tok_open_adapter()
950 ntohs(readw(ti->init_srb + RCV_BUF_LEN_OFST))); in tok_open_adapter()
1097 ntohs(readw(ti->init_srb + SRB_ADDRESS_OFST)), in dir_open_adapter()
1100 ntohs(readw(ti->init_srb + SSB_ADDRESS_OFST)), in dir_open_adapter()
1103 ntohs(readw(ti->init_srb + ARB_ADDRESS_OFST)), in dir_open_adapter()
1106 ntohs(readw(ti->init_srb + ASB_ADDRESS_OFST)), in dir_open_adapter()
1110 err = ntohs(readw(ti->init_srb + OPEN_ERROR_CODE_OFST)); in dir_open_adapter()
[all …]
/drivers/scsi/arm/
Dcumana_1.c141 *laddr++ = readw(dma) | (readw(dma) << 16); in NCR5380_pread()
142 *laddr++ = readw(dma) | (readw(dma) << 16); in NCR5380_pread()
143 *laddr++ = readw(dma) | (readw(dma) << 16); in NCR5380_pread()
144 *laddr++ = readw(dma) | (readw(dma) << 16); in NCR5380_pread()
145 *laddr++ = readw(dma) | (readw(dma) << 16); in NCR5380_pread()
146 *laddr++ = readw(dma) | (readw(dma) << 16); in NCR5380_pread()
147 *laddr++ = readw(dma) | (readw(dma) << 16); in NCR5380_pread()
148 *laddr++ = readw(dma) | (readw(dma) << 16); in NCR5380_pread()
/drivers/serial/
Damba-pl011.c113 status = readw(uap->port.membase + UART01x_FR); in pl011_rx_chars()
115 ch = readw(uap->port.membase + UART01x_DR) | UART_DUMMY_DR_RX; in pl011_rx_chars()
152 status = readw(uap->port.membase + UART01x_FR); in pl011_rx_chars()
195 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; in pl011_modem_status()
223 status = readw(uap->port.membase + UART011_MIS); in pl011_int()
241 status = readw(uap->port.membase + UART011_MIS); in pl011_int()
254 unsigned int status = readw(uap->port.membase + UART01x_FR); in pl01x_tx_empty()
262 unsigned int status = readw(uap->port.membase + UART01x_FR); in pl01x_get_mctrl()
281 cr = readw(uap->port.membase + UART011_CR); in pl011_set_mctrl()
306 lcr_h = readw(uap->port.membase + UART011_LCRH); in pl011_break_ctl()
[all …]
/drivers/char/
Dmoxa.c240 while (readw(ofsAddr + FuncCode) != 0) in moxa_wait_finish()
243 if (readw(ofsAddr + FuncCode) != 0 && printk_ratelimit()) in moxa_wait_finish()
259 rptr = readw(ofsAddr + RXrptr); in moxa_low_water_check()
260 wptr = readw(ofsAddr + RXwptr); in moxa_low_water_check()
261 mask = readw(ofsAddr + RX_mask); in moxa_low_water_check()
470 tmp = readw(baseAddr + C218_key); in moxa_load_bios()
475 tmp = readw(baseAddr + C218_key); in moxa_load_bios()
480 tmp = readw(baseAddr + C320_key); in moxa_load_bios()
483 tmp = readw(baseAddr + C320_status); in moxa_load_bios()
567 if (readw(baseAddr + key) == keycode) in moxa_real_load_code()
[all …]
Depca.c537 head = readw(&bc->tin) & (size - 1); in pc_write()
538 tail = readw(&bc->tout); in pc_write()
540 if (tail != readw(&bc->tout)) in pc_write()
541 tail = readw(&bc->tout); in pc_write()
616 head = readw(&bc->tin) & (ch->txbufsize - 1); in pc_write_room()
617 tail = readw(&bc->tout); in pc_write_room()
619 if (tail != readw(&bc->tout)) in pc_write_room()
620 tail = readw(&bc->tout); in pc_write_room()
658 tail = readw(&bc->tout); in pc_chars_in_buffer()
659 head = readw(&bc->tin); in pc_chars_in_buffer()
[all …]
/drivers/mmc/host/
Dimxmmc.c104 reg = readw(host->base + MMC_REG_STR_STP_CLK); in imxmci_stop_clock()
108 reg = readw(host->base + MMC_REG_STR_STP_CLK); in imxmci_stop_clock()
113 reg = readw(host->base + MMC_REG_STATUS); in imxmci_stop_clock()
116 reg = readw(host->base + MMC_REG_STATUS); in imxmci_stop_clock()
133 reg = readw(host->base + MMC_REG_STR_STP_CLK); in imxmci_start_clock()
143 reg = readw(host->base + MMC_REG_STR_STP_CLK); in imxmci_start_clock()
150 reg = readw(host->base + MMC_REG_STATUS); in imxmci_start_clock()
153 reg = readw(host->base + MMC_REG_STATUS); in imxmci_start_clock()
169 reg = readw(host->base + MMC_REG_STR_STP_CLK); in imxmci_start_clock()
212 *pstat |= readw(host->base + MMC_REG_STATUS); in imxmci_busy_wait_for_status()
[all …]
/drivers/mtd/nand/
Dmxc_nand.c154 tmp = readw(host->regs + NFC_CONFIG1); in mxc_nfc_irq()
172 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) { in wait_op_done()
174 tmp = readw(host->regs + NFC_CONFIG1); in wait_op_done()
179 readw(host->regs + NFC_CONFIG2) & NFC_INT); in wait_op_done()
181 tmp = readw(host->regs + NFC_CONFIG2); in wait_op_done()
187 if (readw(host->regs + NFC_CONFIG2) & NFC_INT) { in wait_op_done()
188 tmp = readw(host->regs + NFC_CONFIG2); in wait_op_done()
240 uint16_t config1 = readw(host->regs + NFC_CONFIG1); in send_prog_page()
266 uint32_t config1 = readw(host->regs + NFC_CONFIG1); in send_read_page()
290 tmp = readw(host->regs + NFC_CONFIG1); in send_read_id()
[all …]
/drivers/char/rio/
Drioboot.c406 OldParmMap = readw(&HostP->__ParmMapR); in RIOBootCodeHOST()
425 …for (wait_count = 0; (wait_count < p->RIOConf.StartupTime) && (readw(&HostP->__ParmMapR) == OldPar… in RIOBootCodeHOST()
426 rio_dprintk(RIO_DEBUG_BOOT, "Checkout %d, 0x%x\n", wait_count, readw(&HostP->__ParmMapR)); in RIOBootCodeHOST()
435 if (readw(&HostP->__ParmMapR) == OldParmMap) { in RIOBootCodeHOST()
436 rio_dprintk(RIO_DEBUG_BOOT, "parmmap 0x%x\n", readw(&HostP->__ParmMapR)); in RIOBootCodeHOST()
444 rio_dprintk(RIO_DEBUG_BOOT, "Running 0x%x\n", readw(&HostP->__ParmMapR)); in RIOBootCodeHOST()
455 ParmMapP = (PARM_MAP __iomem *) RIO_PTR(Cad, readw(&HostP->__ParmMapR)); in RIOBootCodeHOST()
457 ParmMapP = (PARM_MAP __iomem *)(Cad + readw(&HostP->__ParmMapR)); in RIOBootCodeHOST()
465 if (readw(&ParmMapP->links) != 0xFFFF) { in RIOBootCodeHOST()
467 rio_dprintk(RIO_DEBUG_BOOT, "Links = 0x%x\n", readw(&ParmMapP->links)); in RIOBootCodeHOST()
[all …]
Drioinit.c258 if (readw(ram + off) != oldword) { in RIOScrub()
259 … Word Pre Check: WORD at offset 0x%x should have been=%x, was=%x\n",off,oldword, readw(ram + off)); in RIOScrub()
293 if (readw(ram + off) != invword) { in RIOScrub()
294 …ord Inv Check: WORD at offset 0x%x should have been=%x, was=%x\n", off, invword, readw(ram + off)); in RIOScrub()
300 if ( readw(ram + off) != newword ) { in RIOScrub()
301 … Word Check 1: WORD at offset 0x%x should have been=%x, was=%x\n", off, newword, readw(ram + off)); in RIOScrub()
320 if (readw(ram + off) != newword ) { in RIOScrub()
321 … Word Check 2: WORD at offset 0x%x should have been=%x, was=%x\n", off, newword, readw(ram + off)); in RIOScrub()
338 if (readw(ram + off) != swapword) { in RIOScrub()
339 …Word Check 1: WORD at offset 0x%x should have been=%x, was=%x\n", off, swapword, readw(ram + off)); in RIOScrub()
Driocmd.c410 …tk(RIO_DEBUG_CMD, "PACKET information: Check 0x%x (%d)\n", readw(&PacketP->csum), readw(&Packet… in RIOCommandRup()
433 …, "Memory dump cmd (0x%x) from addr 0x%x\n", readb(&PktCmdP->SubCommand), readw(&PktCmdP->SubAddr)… in RIOCommandRup()
436 rio_dprintk(RIO_DEBUG_CMD, "Read register (0x%x)\n", readw(&PktCmdP->SubAddr)); in RIOCommandRup()
592 …if ((UnixRupP->CmdsWaitingP == NULL) && (UnixRupP->CmdPendingP == NULL) && (readw(&UnixRupP->RupP-… in RIOQueueCmdBlk()
599 …HostP->Copy(&CmdBlkP->Packet, RIO_PTR(HostP->Caddr, readw(&UnixRupP->RupP->txpkt)), sizeof(struct … in RIOQueueCmdBlk()
621 if (readw(&UnixRupP->RupP->txcontrol) != TX_RUP_INACTIVE) in RIOQueueCmdBlk()
671 if (readw(&UnixRupP->RupP->rxcontrol) != RX_RUP_INACTIVE) { in RIOPollHostCommands()
674 PacketP = (struct PKT __iomem *) RIO_PTR(HostP->Caddr, readw(&UnixRupP->RupP->rxpkt)); in RIOPollHostCommands()
693 rio_dprintk(RIO_DEBUG_CMD, "Memdump from 0x%x complete\n", readw(&(PacketP->data[6]))); in RIOPollHostCommands()
717 if (readw(&UnixRupP->RupP->handshake) == PHB_HANDSHAKE_SET) { in RIOPollHostCommands()
[all …]
Drioparam.c582 *PktP = tp = (struct PKT __iomem *) RIO_PTR(PortP->Caddr, readw(PortP->TxAdd)); in can_add_transmit()
594 if (readw(PortP->TxAdd) & PKT_IN_USE) { in add_transmit()
597 writew(readw(PortP->TxAdd) | PKT_IN_USE, PortP->TxAdd); in add_transmit()
621 if ((old_end = readw(&HostP->ParmMapP->free_list_end)) != TPNULL) { in put_free_end()
647 if (readw(PortP->RxRemove) & PKT_IN_USE) { in can_remove_receive()
648 *PktP = (struct PKT __iomem *) RIO_PTR(PortP->Caddr, readw(PortP->RxRemove) & ~PKT_IN_USE); in can_remove_receive()
661 writew(readw(PortP->RxRemove) & ~PKT_IN_USE, PortP->RxRemove); in remove_receive()
/drivers/net/
Ddl2k.c242 np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0; in rio_probe1()
686 int_status = readw (ioaddr + IntStatus); in rio_interrupt()
785 writew (readw (ioaddr + TxStartThresh) + 0x10, in tx_error()
792 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0) in tx_error()
812 if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0) in tx_error()
827 writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl); in tx_error()
1012 stat_reg = readw (ioaddr + FramesAbortXSColls); in get_stats()
1016 stat_reg = readw (ioaddr + CarrierSenseErrors); in get_stats()
1022 readw (ioaddr + BcstFramesXmtdOk); in get_stats()
1024 readw (ioaddr + BcstFramesRcvdOk); in get_stats()
[all …]
Dni52.c257 if (readw(&((addr)->cmd_status)) & STAT_COMPL) in wait_for_stat_compl()
636 if ((readw(&cfg_cmd->cmd_status) & (STAT_OK|STAT_COMPL)) != in init586()
639 dev->name, readw(&cfg_cmd->cmd_status)); in init586()
662 if ((readw(&ias_cmd->cmd_status) & (STAT_OK|STAT_COMPL)) != in init586()
664 …printk(KERN_ERR "%s (ni52): individual address setup command failed: %04x\n", dev->name, readw(&ia… in init586()
685 if (!(readw(&tdr_cmd->cmd_status) & STAT_COMPL)) in init586()
690 result = readw(&tdr_cmd->status); in init586()
732 if ((readw(&mc_cmd->cmd_status) & (STAT_COMPL|STAT_OK)) in init586()
957 rbd = make32(readw(&p->rfd_top->rbd_offset)); in ni52_rcv_int()
959 totlen = readw(&rbd->status); in ni52_rcv_int()
[all …]
Dhamachi.c760 dev->name, readw(ioaddr + MiscStatus) & 1 ? 64 : 32, in hamachi_init_one()
762 readw(ioaddr + ANLinkPartnerAbility)); in hamachi_init_one()
835 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_read()
840 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_read()
842 return readw(ioaddr + MII_Rd_Data); in mdio_read()
853 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_write()
860 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_write()
905 fifo_info = (readw(ioaddr + GPIO) & 0x00C0) >> 6; in hamachi_open()
1003 dev->name, readw(ioaddr + RxStatus), readw(ioaddr + TxStatus)); in hamachi_open()
1055 "%4.4x.\n", dev->name, readw(ioaddr + ANStatus), in hamachi_timer()
[all …]
D3c507.c485 readw(shmem + iSCB_STATUS) & 0x8000 ? "IRQ conflict" : in el16_tx_timeout()
559 status = readw(shmem+iSCB_STATUS); in el16_interrupt()
570 unsigned short tx_status = readw(shmem+lp->tx_reap); in el16_interrupt()
747 while (readw(shmem+iSCB_STATUS) == 0) in init_82586_mem()
751 readw(shmem+iSCB_STATUS), readw(shmem+iSCB_CMD)); in init_82586_mem()
762 readw(shmem+iSCB_STATUS)); in init_82586_mem()
824 while ((frame_status = readw(shmem+rx_head)) < 0) { /* Command complete */ in el16_rx()
826 ushort rfd_cmd = readw(read_frame+2); in el16_rx()
827 ushort next_rx_frame = readw(read_frame+4); in el16_rx()
828 ushort data_buffer_addr = readw(read_frame+6); in el16_rx()
[all …]
/drivers/dma/
Dioat_dca.c338 readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET); in ioat2_dca_add_requester()
364 readw(ioatdca->dca_base + IOAT_DCA_GREQID_OFFSET); in ioat2_dca_remove_requester()
399 global_req_table = readw(iobase + dca_offset + IOAT_DCA_GREQID_OFFSET); in ioat2_dca_count_dca_slots()
426 dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET); in ioat2_dca_init()
446 csi_fsb_control = readw(ioatdca->dca_base + IOAT_FSB_CAP_ENABLE_OFFSET); in ioat2_dca_init()
452 pcie_control = readw(ioatdca->dca_base + IOAT_PCI_CAP_ENABLE_OFFSET); in ioat2_dca_init()
512 readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); in ioat3_dca_add_requester()
538 readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); in ioat3_dca_remove_requester()
593 global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET); in ioat3_dca_count_dca_slots()
628 dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET); in ioat3_dca_init()
[all …]
/drivers/staging/comedi/drivers/
Dicp_multi.c269 readw(devpriv->io_addr + ICP_MULTI_ADC_CSR), in icp_multi_insn_read_ai()
282 readw(devpriv->io_addr + ICP_MULTI_ADC_CSR)); in icp_multi_insn_read_ai()
289 readw(devpriv->io_addr + ICP_MULTI_ADC_CSR)); in icp_multi_insn_read_ai()
295 if (!(readw(devpriv->io_addr + in icp_multi_insn_read_ai()
303 readw(devpriv->io_addr + in icp_multi_insn_read_ai()
332 (readw(devpriv->io_addr + ICP_MULTI_AI) >> 4) & 0x0fff; in icp_multi_insn_read_ai()
402 if (!(readw(devpriv->io_addr + in icp_multi_insn_write_ao()
410 readw(devpriv->io_addr + in icp_multi_insn_write_ao()
511 data[1] = readw(devpriv->io_addr + ICP_MULTI_DI); in icp_multi_insn_bits_di()
550 data[1] = readw(devpriv->io_addr + ICP_MULTI_DI); in icp_multi_insn_bits_do()
[all …]
Dme_daq.c342 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_A); in me_dio_insn_bits()
350 data[1] |= readw(dev_private->me_regbase + ME_DIO_PORT_B) << 16; in me_dio_insn_bits()
405 readw(dev_private->me_regbase + ME_ADC_START); in me_ai_insn_read()
409 if (!(readw(dev_private->me_regbase + ME_STATUS) & 0x0004)) in me_ai_insn_read()
415 (readw(dev_private->me_regbase + in me_ai_insn_read()
505 readw(dev_private->me_regbase + ME_DAC_CONTROL_UPDATE); in me_ao_insn_write()
516 readw(dev_private->me_regbase + ME_DAC_UPDATE); in me_ao_insn_write()
556 value = readw(dev_private->me_regbase + XILINX_DOWNLOAD_RESET); in me2600_xilinx_download()
/drivers/atm/
Diphase.c1009 tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
1011 tcq_wr_ptr, readw(iadev->seg_ram+tcq_wr_ptr),
1012 readw(iadev->seg_ram+tcq_wr_ptr-2));
1015 tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);
1016 tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);
1021 printk("TCQ slot %d desc = %d Addr = %p\n", i++, readw(tmp), tmp);
1043 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1048 vci = readw(iadev->reass_ram+excpq_rd_ptr);
1049 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1052 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
[all …]
/drivers/ata/
Dsata_vsc.c206 tf->device = readw(ioaddr->device_addr); in vsc_sata_tf_read()
207 feature = readw(ioaddr->error_addr); in vsc_sata_tf_read()
208 nsect = readw(ioaddr->nsect_addr); in vsc_sata_tf_read()
209 lbal = readw(ioaddr->lbal_addr); in vsc_sata_tf_read()
210 lbam = readw(ioaddr->lbam_addr); in vsc_sata_tf_read()
211 lbah = readw(ioaddr->lbah_addr); in vsc_sata_tf_read()
Dsata_nv.c593 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
596 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
604 tmp = readw(mmio + NV_ADMA_CTL); in nv_adma_register_mode()
608 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
611 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
634 tmp = readw(mmio + NV_ADMA_CTL); in nv_adma_mode()
637 status = readw(mmio + NV_ADMA_STAT); in nv_adma_mode()
641 status = readw(mmio + NV_ADMA_STAT); in nv_adma_mode()
951 status = readw(mmio + NV_ADMA_STAT); in nv_adma_interrupt()
957 readw(mmio + NV_ADMA_STAT); /* flush posted write */ in nv_adma_interrupt()
[all …]
Dsata_svw.c188 tf->device = readw(ioaddr->device_addr); in k2_sata_tf_read()
189 feature = readw(ioaddr->error_addr); in k2_sata_tf_read()
190 nsect = readw(ioaddr->nsect_addr); in k2_sata_tf_read()
191 lbal = readw(ioaddr->lbal_addr); in k2_sata_tf_read()
192 lbam = readw(ioaddr->lbam_addr); in k2_sata_tf_read()
193 lbah = readw(ioaddr->lbah_addr); in k2_sata_tf_read()

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