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Searched refs:reg_base (Results 1 – 25 of 104) sorted by relevance

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/drivers/video/exynos/
Dexynos_dp_reg.c33 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
35 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
37 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
39 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute()
47 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video()
49 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video()
63 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); in exynos_dp_lane_swap()
71 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); in exynos_dp_init_analog_param()
74 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); in exynos_dp_init_analog_param()
77 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); in exynos_dp_init_analog_param()
[all …]
Dexynos_mipi_dsi_lowlevel.c35 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_func_reset()
39 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_func_reset()
46 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_sw_reset()
50 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_sw_reset()
57 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_sw_reset_release()
61 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_sw_reset_release()
66 return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) & in exynos_mipi_dsi_get_sw_reset_release()
74 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK); in exynos_mipi_dsi_read_interrupt_mask()
89 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK); in exynos_mipi_dsi_set_interrupt_mask()
97 reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); in exynos_mipi_dsi_init_fifo_pointer()
[all …]
/drivers/video/mmp/hw/
Dmmp_spi.c47 void *reg_base = in lcd_spi_write() local
51 writel_relaxed(~SPI_IRQ_MASK, reg_base + SPU_IRQ_ISR); in lcd_spi_write()
55 writel_relaxed((u8)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
58 writel_relaxed((u16)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
61 writel_relaxed((u32)data, reg_base + LCD_SPU_SPI_TXDATA); in lcd_spi_write()
68 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
71 writel(tmp, reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
73 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
76 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
84 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
[all …]
/drivers/ide/
Dopti621.c29 static int reg_base; variable
40 inw(reg_base + 1); in write_reg()
41 inw(reg_base + 1); in write_reg()
42 outb(3, reg_base + 2); in write_reg()
43 outb(value, reg_base + reg); in write_reg()
44 outb(0x83, reg_base + 2); in write_reg()
56 inw(reg_base + 1); in read_reg()
57 inw(reg_base + 1); in read_reg()
58 outb(3, reg_base + 2); in read_reg()
59 ret = inb(reg_base + reg); in read_reg()
[all …]
/drivers/spi/
Dspi-fsl-espi.c90 struct fsl_espi_reg *reg_base = mspi->reg_base; in fsl_espi_change_mode() local
91 __be32 __iomem *mode = &reg_base->csmode[spi->chip_select]; in fsl_espi_change_mode()
92 __be32 __iomem *espi_mode = &reg_base->mode; in fsl_espi_change_mode()
207 struct fsl_espi_reg *reg_base = mspi->reg_base; in fsl_espi_cpu_bufs() local
212 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE); in fsl_espi_cpu_bufs()
216 mpc8xxx_spi_write_reg(&reg_base->transmit, word); in fsl_espi_cpu_bufs()
224 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; in fsl_espi_bufs() local
247 mpc8xxx_spi_write_reg(&reg_base->command, in fsl_espi_bufs()
257 mpc8xxx_spi_write_reg(&reg_base->mask, 0); in fsl_espi_bufs()
459 struct fsl_espi_reg *reg_base; in fsl_espi_setup() local
[all …]
Dspi-fsl-spi.c90 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_change_mode() local
91 __be32 __iomem *mode = &reg_base->mode; in fsl_spi_change_mode()
298 struct fsl_spi_reg *reg_base = mspi->reg_base; in fsl_spi_cpu_bufs() local
303 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE); in fsl_spi_cpu_bufs()
307 mpc8xxx_spi_write_reg(&reg_base->transmit, word); in fsl_spi_cpu_bufs()
316 struct fsl_spi_reg *reg_base; in fsl_spi_bufs() local
321 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_bufs()
354 mpc8xxx_spi_write_reg(&reg_base->mask, 0); in fsl_spi_bufs()
420 struct fsl_spi_reg *reg_base; in fsl_spi_setup() local
436 reg_base = mpc8xxx_spi->reg_base; in fsl_spi_setup()
[all …]
/drivers/video/
Dpxa168fb.c291 writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV); in set_clock_divider()
301 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); in set_dma_control0()
326 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0); in set_dma_control0()
338 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1); in set_dma_control1()
348 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1); in set_dma_control1()
361 writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0); in set_graphics_start()
373 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL) & 0x00000001; in set_dumb_panel_control()
386 writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL); in set_dumb_panel_control()
399 writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL); in set_dumb_screen_dimensions()
425 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL); in pxa168fb_set_par()
[all …]
Dgoldfishfb.c89 void __iomem *reg_base; member
106 status = readl(fb->reg_base + FB_INT_STATUS); in goldfish_fb_interrupt()
174 writel(fb->rotation, fb->reg_base + FB_SET_ROTATION); in goldfish_fb_set_par()
191 fb->reg_base + FB_SET_BASE); in goldfish_fb_pan_display()
205 writel(1, fb->reg_base + FB_SET_BLANK); in goldfish_fb_blank()
208 writel(0, fb->reg_base + FB_SET_BLANK); in goldfish_fb_blank()
252 fb->reg_base = ioremap(r->start, PAGE_SIZE); in goldfish_fb_probe()
253 if (fb->reg_base == NULL) { in goldfish_fb_probe()
264 width = readl(fb->reg_base + FB_GET_WIDTH); in goldfish_fb_probe()
265 height = readl(fb->reg_base + FB_GET_HEIGHT); in goldfish_fb_probe()
[all …]
/drivers/i2c/busses/
Di2c-mv64xxx.c94 void __iomem *reg_base; member
127 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET); in mv64xxx_i2c_hw_init()
129 drv_data->reg_base + MV64XXX_I2C_REG_BAUD); in mv64xxx_i2c_hw_init()
130 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR); in mv64xxx_i2c_hw_init()
131 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR); in mv64xxx_i2c_hw_init()
133 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); in mv64xxx_i2c_hw_init()
253 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); in mv64xxx_i2c_do_action()
260 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); in mv64xxx_i2c_do_action()
265 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); in mv64xxx_i2c_do_action()
270 drv_data->reg_base + MV64XXX_I2C_REG_DATA); in mv64xxx_i2c_do_action()
[all …]
Di2c-pca-platform.c31 void __iomem *reg_base; member
46 return ioread8(i2c->reg_base + reg); in i2c_pca_pf_readbyte8()
52 return ioread8(i2c->reg_base + reg * 2); in i2c_pca_pf_readbyte16()
58 return ioread8(i2c->reg_base + reg * 4); in i2c_pca_pf_readbyte32()
64 iowrite8(val, i2c->reg_base + reg); in i2c_pca_pf_writebyte8()
70 iowrite8(val, i2c->reg_base + reg * 2); in i2c_pca_pf_writebyte16()
76 iowrite8(val, i2c->reg_base + reg * 4); in i2c_pca_pf_writebyte32()
165 i2c->reg_base = ioremap(res->start, resource_size(res)); in i2c_pca_pf_probe()
166 if (!i2c->reg_base) { in i2c_pca_pf_probe()
250 iounmap(i2c->reg_base); in i2c_pca_pf_probe()
[all …]
/drivers/staging/tidspbridge/core/
Dwdt.c45 value = __raw_readl(dsp_wdt.reg_base + OMAP3_WDT3_ISR_OFFSET); in dsp_wdt_isr()
46 __raw_writel(value, dsp_wdt.reg_base + OMAP3_WDT3_ISR_OFFSET); in dsp_wdt_isr()
57 dsp_wdt.reg_base = ioremap(OMAP34XX_WDT3_BASE, SZ_4K); in dsp_wdt_init()
58 if (!dsp_wdt.reg_base) in dsp_wdt_init()
115 if (dsp_wdt.reg_base) in dsp_wdt_exit()
116 iounmap(dsp_wdt.reg_base); in dsp_wdt_exit()
117 dsp_wdt.reg_base = NULL; in dsp_wdt_exit()
134 tmp = __raw_readl(dsp_wdt.reg_base + OMAP3_WDT3_ISR_OFFSET); in dsp_wdt_enable()
135 __raw_writel(tmp, dsp_wdt.reg_base + OMAP3_WDT3_ISR_OFFSET); in dsp_wdt_enable()
/drivers/net/can/sja1000/
Dsja1000_platform.c42 return ioread8(priv->reg_base + reg); in sp_read_reg8()
47 iowrite8(val, priv->reg_base + reg); in sp_write_reg8()
52 return ioread8(priv->reg_base + reg * 2); in sp_read_reg16()
57 iowrite8(val, priv->reg_base + reg * 2); in sp_write_reg16()
62 return ioread8(priv->reg_base + reg * 4); in sp_read_reg32()
67 iowrite8(val, priv->reg_base + reg * 4); in sp_write_reg32()
116 priv->reg_base = addr; in sp_probe()
149 DRV_NAME, priv->reg_base, dev->irq); in sp_probe()
171 if (priv->reg_base) in sp_remove()
172 iounmap(priv->reg_base); in sp_remove()
Dsja1000_isa.c82 return readb(priv->reg_base + reg); in sja1000_isa_mem_read_reg()
88 writeb(val, priv->reg_base + reg); in sja1000_isa_mem_write_reg()
93 return inb((unsigned long)priv->reg_base + reg); in sja1000_isa_port_read_reg()
99 outb(val, (unsigned long)priv->reg_base + reg); in sja1000_isa_port_write_reg()
105 unsigned long base = (unsigned long)priv->reg_base; in sja1000_isa_port_read_reg_indirect()
114 unsigned long base = (unsigned long)priv->reg_base; in sja1000_isa_port_write_reg_indirect()
162 priv->reg_base = base; in sja1000_isa_probe()
167 priv->reg_base = (void __iomem *)port[idx]; in sja1000_isa_probe()
211 DRV_NAME, priv->reg_base, dev->irq); in sja1000_isa_probe()
236 iounmap(priv->reg_base); in sja1000_isa_remove()
Dpeak_pci.c147 void __iomem *reg_base; /* first channel base address */ member
402 int c = (priv->reg_base - card->reg_base) / PEAK_PCI_CHAN_SIZE; in peak_pciec_write_reg()
457 card->reg_base = priv->reg_base; in peak_pciec_probe()
530 return readb(priv->reg_base + (port << 2)); in peak_pci_read_reg()
536 writeb(val, priv->reg_base + (port << 2)); in peak_pci_write_reg()
555 void __iomem *cfg_base, *reg_base; in peak_pci_probe() local
594 reg_base = pci_iomap(pdev, 1, PEAK_PCI_CHAN_SIZE * channels); in peak_pci_probe()
595 if (!reg_base) { in peak_pci_probe()
624 priv->reg_base = reg_base + i * PEAK_PCI_CHAN_SIZE; in peak_pci_probe()
673 dev->name, priv->reg_base, chan->cfg_base, dev->irq); in peak_pci_probe()
[all …]
/drivers/clk/mvebu/
Dclk-cpu.c30 void __iomem *reg_base; member
45 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_recalc_rate()
73 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) in clk_cpu_set_rate()
76 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_set_rate()
80 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) in clk_cpu_set_rate()
82 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); in clk_cpu_set_rate()
85 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) in clk_cpu_set_rate()
87 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); in clk_cpu_set_rate()
92 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); in clk_cpu_set_rate()
148 cpuclk[cpu].reg_base = clock_complex_base; in of_cpu_clk_setup()
/drivers/dma/ioat/
Ddma.h44 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
81 void __iomem *reg_base; member
104 void __iomem *reg_base; member
241 status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver)); in ioat_chansts_32()
242 status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver)); in ioat_chansts_32()
258 status = readq(chan->reg_base + IOAT_CHANSTS_OFFSET(ver)); in ioat_chansts()
273 writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); in ioat_start()
283 return readl(chan->reg_base + IOAT_CHANERR_OFFSET); in ioat_chanerr()
290 writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); in ioat_suspend()
297 writeb(IOAT_CHANCMD_RESET, chan->reg_base + IOAT_CHANCMD_OFFSET(ver)); in ioat_reset()
[all …]
/drivers/input/keyboard/
Dnomadik-ske-keypad.c65 void __iomem *reg_base; member
81 ret = readl(keypad->reg_base + addr); in ske_keypad_set_bits()
84 writel(ret, keypad->reg_base + addr); in ske_keypad_set_bits()
100 while ((readl(keypad->reg_base + SKE_RIS) != 0x00000000) && timeout--) in ske_keypad_chip_init()
112 value = readl(keypad->reg_base + SKE_DBCR); in ske_keypad_chip_init()
115 writel(value, keypad->reg_base + SKE_DBCR); in ske_keypad_chip_init()
156 ske_ris = readl(keypad->reg_base + SKE_RIS); in ske_keypad_report()
180 ske_asr = readl(keypad->reg_base + SKE_ASR0 + (4 * i)); in ske_keypad_read_data()
207 while ((readl(keypad->reg_base + SKE_CR) & SKE_KPASON) && --timeout) in ske_keypad_irq()
214 while ((readl(keypad->reg_base + SKE_RIS)) && --timeout) in ske_keypad_irq()
[all …]
/drivers/usb/musb/
Dda8xx.c149 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_enable() local
156 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask); in da8xx_musb_enable()
159 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG, in da8xx_musb_enable()
168 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_disable() local
170 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG, in da8xx_musb_disable()
174 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0); in da8xx_musb_disable()
291 void __iomem *reg_base = musb->ctrl_base; in da8xx_musb_interrupt() local
305 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG); in da8xx_musb_interrupt()
309 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status); in da8xx_musb_interrupt()
325 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG); in da8xx_musb_interrupt()
[all …]
Dam35x.c99 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_enable() local
106 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); in am35x_musb_enable()
107 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); in am35x_musb_enable()
110 musb_writel(reg_base, CORE_INTR_SRC_SET_REG, in am35x_musb_enable()
119 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_disable() local
121 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); in am35x_musb_disable()
122 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, in am35x_musb_disable()
125 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); in am35x_musb_disable()
219 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_interrupt() local
231 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); in am35x_musb_interrupt()
[all …]
Dmusb_dsps.c178 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_enable() local
186 dsps_writel(reg_base, wrp->epintr_set, epmask); in dsps_musb_enable()
187 dsps_writel(reg_base, wrp->coreintr_set, coremask); in dsps_musb_enable()
189 dsps_writel(reg_base, wrp->coreintr_set, in dsps_musb_enable()
202 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_disable() local
204 dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap); in dsps_musb_disable()
205 dsps_writel(reg_base, wrp->epintr_clear, in dsps_musb_disable()
208 dsps_writel(reg_base, wrp->eoi, 0); in dsps_musb_disable()
300 void __iomem *reg_base = musb->ctrl_base; in dsps_interrupt() local
312 epintr = dsps_readl(reg_base, wrp->epintr_status); in dsps_interrupt()
[all …]
/drivers/ntb/
Dntb_hw.c538 ndev->reg_ofs.pdb = ndev->reg_base + SNB_PDOORBELL_OFFSET; in ntb_xeon_setup()
539 ndev->reg_ofs.pdb_mask = ndev->reg_base + SNB_PDBMSK_OFFSET; in ntb_xeon_setup()
540 ndev->reg_ofs.sbar2_xlat = ndev->reg_base + SNB_SBAR2XLAT_OFFSET; in ntb_xeon_setup()
541 ndev->reg_ofs.sbar4_xlat = ndev->reg_base + SNB_SBAR4XLAT_OFFSET; in ntb_xeon_setup()
542 ndev->reg_ofs.lnk_cntl = ndev->reg_base + SNB_NTBCNTL_OFFSET; in ntb_xeon_setup()
543 ndev->reg_ofs.lnk_stat = ndev->reg_base + SNB_LINK_STATUS_OFFSET; in ntb_xeon_setup()
544 ndev->reg_ofs.spad_read = ndev->reg_base + SNB_SPAD_OFFSET; in ntb_xeon_setup()
545 ndev->reg_ofs.spci_cmd = ndev->reg_base + SNB_PCICMD_OFFSET; in ntb_xeon_setup()
548 ndev->reg_ofs.sdb = ndev->reg_base + SNB_B2B_DOORBELL_OFFSET; in ntb_xeon_setup()
549 ndev->reg_ofs.spad_write = ndev->reg_base + SNB_B2B_SPAD_OFFSET; in ntb_xeon_setup()
[all …]
/drivers/clocksource/
Dexynos_mct.c77 static void __iomem *reg_base; variable
94 __raw_writel(value, reg_base + offset); in exynos4_mct_write()
144 if (__raw_readl(reg_base + stat_addr) & mask) { in exynos4_mct_write()
145 __raw_writel(mask, reg_base + stat_addr); in exynos4_mct_write()
160 reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); in exynos4_mct_frc_start()
168 u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); in exynos4_frc_read()
172 lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L); in exynos4_frc_read()
173 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); in exynos4_frc_read()
205 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); in exynos4_mct_comp0_stop()
218 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); in exynos4_mct_comp0_start()
[all …]
/drivers/dma/
Dmmp_tdma.c119 unsigned long reg_base; member
138 writel(phys, tdmac->reg_base + TDNDPR); in mmp_tdma_chan_set_desc()
139 writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND, in mmp_tdma_chan_set_desc()
140 tdmac->reg_base + TDCR); in mmp_tdma_chan_set_desc()
146 writel(TDIMR_COMP, tdmac->reg_base + TDIMR); in mmp_tdma_enable_chan()
148 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, in mmp_tdma_enable_chan()
149 tdmac->reg_base + TDCR); in mmp_tdma_enable_chan()
155 writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN, in mmp_tdma_disable_chan()
156 tdmac->reg_base + TDCR); in mmp_tdma_disable_chan()
162 writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN, in mmp_tdma_resume_chan()
[all …]
/drivers/staging/media/davinci_vpfe/
Ddm365_ipipe_hw.c75 u32 reg_base; in rsz_set_rsz_regs() local
85 reg_base = RSZ_EN_A; in rsz_set_rsz_regs()
89 reg_base = RSZ_EN_B; in rsz_set_rsz_regs()
94 regw_rsz(rsz_base, params->oper_mode, reg_base + RSZ_MODE); in rsz_set_rsz_regs()
97 regw_rsz(rsz_base, val, reg_base + RSZ_420); in rsz_set_rsz_regs()
100 reg_base + RSZ_I_VPS); in rsz_set_rsz_regs()
102 reg_base + RSZ_I_HPS); in rsz_set_rsz_regs()
104 reg_base + RSZ_O_VSZ); in rsz_set_rsz_regs()
106 reg_base + RSZ_O_HSZ); in rsz_set_rsz_regs()
108 reg_base + RSZ_V_PHS_Y); in rsz_set_rsz_regs()
[all …]
/drivers/clk/samsung/
Dclk-exynos5440.c108 void __iomem *reg_base; in exynos5440_clk_init() local
110 reg_base = of_iomap(np, 0); in exynos5440_clk_init()
111 if (!reg_base) { in exynos5440_clk_init()
117 samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0); in exynos5440_clk_init()
121 samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10); in exynos5440_clk_init()
122 samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10); in exynos5440_clk_init()

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