| /arch/score/include/asm/ |
| D | asmmacro.h | 10 mv r31, r0
18 mv r30, r0
19 addri r0, r31, -PT_SIZE
21 sw r30, [r0, PT_R0]
23 sw r1, [r0, PT_R1]
25 sw r2, [r0, PT_R2]
26 sw r3, [r0, PT_R3]
27 sw r4, [r0, PT_R4]
28 sw r5, [r0, PT_R5]
29 sw r6, [r0, PT_R6]
[all …]
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| /arch/arm/lib/ |
| D | delay-loop.S | 26 mul r0, r2, r0
27 ENTRY(__loop_const_udelay) @ 0 <= r0 <= 0x7fffff06
31 add r0, r0, r1, lsr #32-14
32 mov r0, r0, lsr #14 @ max = 0x0001ffff
35 mul r0, r2, r0 @ max = 2^32-1
36 add r0, r0, r1, lsr #32-6
37 movs r0, r0, lsr #6
47 subs r0, r0, #1
50 subs r0, r0, #1
52 subs r0, r0, #1
[all …]
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| D | getuser.S | 36 check_uaccess r0, 1, r1, r2, __get_user_bad
37 1: TUSER(ldrb) r2, [r0]
38 mov r0, #0
43 check_uaccess r0, 2, r1, r2, __get_user_bad
46 2: ldrbt r2, [r0], #1
47 3: ldrbt rb, [r0], #0
49 rb .req r0
50 2: ldrb r2, [r0]
51 3: ldrb rb, [r0, #1]
58 mov r0, #0
[all …]
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| D | putuser.S | 36 check_uaccess r0, 1, r1, ip, __put_user_bad
37 1: TUSER(strb) r2, [r0]
38 mov r0, #0
43 check_uaccess r0, 2, r1, ip, __put_user_bad
47 2: TUSER(strb) r2, [r0]
48 3: TUSER(strb) ip, [r0, #1]
50 2: TUSER(strb) ip, [r0]
51 3: TUSER(strb) r2, [r0, #1]
55 2: TUSER(strb) r2, [r0], #1
56 3: TUSER(strb) ip, [r0]
[all …]
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| /arch/sh/lib/ |
| D | checksum.S | 51 mov r4, r0
52 tst #3, r0 ! Check alignment.
56 tst #1, r0 ! Check alignment.
63 mov.b @r4+, r0
64 extu.b r0, r0
65 addc r0, r6 ! t=0 from previous tst
66 mov r6, r0
68 shlr16 r0
69 shlr8 r0
70 or r0, r6
[all …]
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| D | ashrsi3.S | 51 ! r0: Result
62 mov #31,r0
63 and r0,r5
64 mova ashrsi3_table,r0
65 mov.b @(r0,r5),r5
67 add r5,r0
68 jmp @r0
72 mov r4,r0
110 rotcl r0
112 subc r0,r0
[all …]
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| D | ashlsi3.S | 51 ! r0: Result
61 mov #31,r0
62 and r0,r5
63 mova ashlsi3_table,r0
64 mov.b @(r0,r5),r5
66 add r5,r0
67 jmp @r0
71 mov r4,r0
109 shll2 r0
111 shll2 r0
[all …]
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| D | lshrsi3.S | 51 ! r0: Result
61 mov #31,r0
62 and r0,r5
63 mova lshrsi3_table,r0
64 mov.b @(r0,r5),r5
66 add r5,r0
67 jmp @r0
71 mov r4,r0
109 shlr2 r0
111 shlr2 r0
[all …]
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| /arch/arm/mach-pxa/ |
| D | standby.S | 22 ldr r0, =PSSR
31 str r1, [r0] @ make sure PSSR_PH/STS are clear
64 mcr p14, 0, r0, c7, c0, 0
69 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
70 bic r0, r0, #PXA3_DDR_HCAL_HCEN
71 str r0, [r1, #PXA3_DDR_HCAL]
72 1: ldr r0, [r1, #PXA3_DDR_HCAL]
73 tst r0, #PXA3_DDR_HCAL_HCEN
76 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
77 orr r0, r0, #PXA3_RCOMP_SWEVAL
[all …]
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| /arch/arm/mm/ |
| D | cache-v6.S | 39 mov r0, #0
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
65 mov r0, #0
67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
[all …]
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| D | proc-arm946.S | 47 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
48 bic r0, r0, #0x00001000 @ i-cache
49 bic r0, r0, #0x00000004 @ d-cache
50 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 ret r0
77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
86 mov r0, #0
87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
135 sub r3, r1, r0 @ calculate total size
141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
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| D | cache-fa.S | 47 mov r0, #0
48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
89 sub r3, r1, r0 @ calculate total size
94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
95 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
96 add r0, r0, #CACHE_DLINESIZE
97 cmp r0, r1
129 bic r0, r0, #CACHE_DLINESIZE - 1
130 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
131 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
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| D | proc-arm740.S | 41 mrc p15, 0, r0, c1, c0, 0
42 bic r0, r0, #0x3f000000 @ bank/f/lock/s
43 bic r0, r0, #0x0000000c @ w-buffer/cache
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
59 ret r0
65 mov r0, #0
66 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
68 mcr p15, 0, r0, c6, c3 @ disable area 3~7
69 mcr p15, 0, r0, c6, c4
70 mcr p15, 0, r0, c6, c5
[all …]
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| D | proc-arm925.S | 95 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
96 bic r0, r0, #0x1000 @ ...i............
97 bic r0, r0, #0x000e @ ............wca.
98 mcr p15, 0, r0, c1, c0, 0 @ disable caches
132 ret r0
141 mov r0, #0
143 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
146 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
156 mov r0, #0
157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
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| /arch/powerpc/lib/ |
| D | checksum_64.S | 28 lwz r0,0(r3)
31 addc r0,r0,r5
35 adde r0,r0,r4
37 addze r0,r0 /* add in final carry */
38 rldicl r4,r0,32,0 /* fold two 32-bit halves together */
39 add r0,r0,r4
40 srdi r0,r0,32
41 rlwinm r3,r0,16,0,31 /* fold two halves together */
42 add r3,r0,r3
56 addc r0,r3,r4 /* add 4 32-bit words together */
[all …]
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| /arch/tile/kernel/ |
| D | relocate_kernel_32.S | 27 move r30, r0 /* page list */
41 moveli r0, 'r'
44 moveli r0, '_'
47 moveli r0, 'n'
50 moveli r0, '_'
53 moveli r0, 'k'
56 moveli r0, '\n'
90 move r0, zero /* cache_pa */
125 seqi r0, r9, 0x1 /* IND_DESTINATION */
126 bzt r0, .Ltry2
[all …]
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| D | relocate_kernel_64.S | 27 move r30, r0 /* page list */
42 moveli r0, 'r'
45 moveli r0, '_'
48 moveli r0, 'n'
51 moveli r0, '_'
54 moveli r0, 'k'
57 moveli r0, '\n'
91 move r0, zero /* cache_pa */
128 cmpeqi r0, r9, 0x1 /* IND_DESTINATION */
129 beqzt r0, .Ltry2
[all …]
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| /arch/sh/kernel/cpu/shmobile/ |
| D | sleep.S | 24 #define k0 r0
37 stc vbr, r0
38 mov.l r0, @(SH_SLEEP_VBR, r5)
44 sts pr, r0
45 mov.l r0, @(SH_SLEEP_SPC, r5)
48 stc sr, r0
49 mov.l r0, @(SH_SLEEP_SR, r5)
52 mov.l @(SH_SLEEP_MODE, r5), r0
53 tst #SUSP_SH_REGS, r0
96 mov #SH_SLEEP_REG_STBCR, r0
[all …]
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| /arch/sh/kernel/cpu/sh5/ |
| D | switchto.S | 45 movi FRAME_SIZE, r0
46 sub.l r15, r0, r15
56 addi.l r1, 24, r0 ! base of pt_regs.regs
57 addi.l r0, (63*8), r8 ! base of pt_regs.trregs
66 st.q r0, ( 9*8), r9
67 st.q r0, (10*8), r10
68 st.q r0, (11*8), r11
69 st.q r0, (12*8), r12
70 st.q r0, (13*8), r13
71 st.q r0, (14*8), r14 ! for unwind, want to look as though we took a trap at
[all …]
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| /arch/m32r/lib/ |
| D | checksum.S | 55 ; r0: unsigned char *buff
60 and3 r7, r0, #1 ; Check alignment.
63 ldub r4, @r0 || addi r0, #1
65 cmp r0, r0 || addi r1, #-1
70 and3 r4, r0, #2 ; Check alignment.
73 cmp r0, r0 || addi r1, #-2
79 lduh r4, @r0 || ldi r3, #0
80 addx r2, r4 || addi r0, #2
85 cmp r0, r0 ; clear c-bit
90 1: ld r3, @r0+
[all …]
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| /arch/arc/lib/ |
| D | strcmp.S | 19 or r2,r0,r1
25 ld.ab r2,[r0,4]
34 xor r0,r2,r3 ; mask for difference
35 sub_s r1,r0,1
36 bic_s r0,r0,r1 ; mask for least significant difference bit
37 sub r1,r5,r0
38 xor r0,r5,r1 ; mask for least significant difference byte
39 and_s r2,r2,r0
40 and_s r3,r3,r0
43 mov_s r0,1
[all …]
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| /arch/powerpc/kernel/ |
| D | cpu_setup_ppc970.S | 21 mfmsr r0
22 rldicl. r0,r0,4,63
29 li r0,0
31 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
32 rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
38 rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
45 mfspr r0,SPRN_HID1
48 or r0,r0,r3
49 mtspr SPRN_HID1,r0
50 mtspr SPRN_HID1,r0
[all …]
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| /arch/unicore32/mm/ |
| D | tlb-ucv2.S | 30 mov r0, r0 >> #PAGE_SHIFT @ align address
31 mov r0, r0 << #PAGE_SHIFT
34 movc p0.c6, r0, #3
40 movc p0.c6, r0, #5
43 add r0, r0, #PAGE_SZ
44 csub.a r0, r1
47 movc p0.c6, r0, #2
53 movc p0.c6, r0, #4
69 mov r0, r0 >> #PAGE_SHIFT @ align address
70 mov r0, r0 << #PAGE_SHIFT
[all …]
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| /arch/arm/mach-omap2/ |
| D | sleep44xx.S | 69 cmp r0, #0x0
77 ldr r9, [r0, #OMAP_TYPE_OFFSET]
80 mov r0, #SCU_PM_NORMAL
94 mrc p15, 0, r0, c1, c0, 0
95 bic r0, r0, #(1 << 2) @ Disable the C bit
96 mcr p15, 0, r0, c1, c0, 0
115 mov r8, r0
119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
120 ands r0, r0, #0x0f
121 ldreq r0, [r8, #SCU_OFFSET0]
[all …]
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| /arch/m32r/mm/ |
| D | page.S | 27 ld r3, @r0 /* cache line allocate */
34 st r4, @r0
35 st r5, @+r0
36 st r6, @+r0
37 st r7, @+r0
39 addi r0, #4
43 ld r3, @r0 /* cache line allocate */
47 st r4, @r0
48 st r5, @+r0
49 st r6, @+r0
[all …]
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