Home
last modified time | relevance | path

Searched refs:ah (Results 1 – 25 of 166) sorted by relevance

1234567

/drivers/net/wireless/ath/ath9k/
Dar9003_hw.c40 static void ar9003_hw_init_mode_regs(struct ath_hw *ah) in ar9003_hw_init_mode_regs() argument
42 if (AR_SREV_9330_11(ah)) { in ar9003_hw_init_mode_regs()
44 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], in ar9003_hw_init_mode_regs()
46 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], in ar9003_hw_init_mode_regs()
50 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], in ar9003_hw_init_mode_regs()
52 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], in ar9003_hw_init_mode_regs()
56 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], in ar9003_hw_init_mode_regs()
60 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], in ar9003_hw_init_mode_regs()
62 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], in ar9003_hw_init_mode_regs()
66 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9003_hw_init_mode_regs()
[all …]
Dhw.c31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
38 static void ath9k_hw_set_clockrate(struct ath_hw *ah) in ath9k_hw_set_clockrate() argument
40 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_clockrate()
41 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_clockrate()
45 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) in ath9k_hw_set_clockrate()
51 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) in ath9k_hw_set_clockrate()
68 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) in ath9k_hw_mac_to_clks() argument
70 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_mac_to_clks()
75 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) in ath9k_hw_wait() argument
82 if ((REG_READ(ah, reg) & mask) == val) in ath9k_hw_wait()
[all …]
Dhw-ops.h24 static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah, in ath9k_hw_configpcipowersave() argument
27 if (!ah->aspm_enabled) in ath9k_hw_configpcipowersave()
30 ath9k_hw_ops(ah)->config_pci_powersave(ah, power_off); in ath9k_hw_configpcipowersave()
33 static inline void ath9k_hw_rxena(struct ath_hw *ah) in ath9k_hw_rxena() argument
35 ath9k_hw_ops(ah)->rx_enable(ah); in ath9k_hw_rxena()
38 static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds, in ath9k_hw_set_desc_link() argument
41 ath9k_hw_ops(ah)->set_desc_link(ds, link); in ath9k_hw_set_desc_link()
44 static inline bool ath9k_hw_calibrate(struct ath_hw *ah, in ath9k_hw_calibrate() argument
49 return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal); in ath9k_hw_calibrate()
52 static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked, in ath9k_hw_getisr() argument
[all …]
Dar9002_hw.c26 static int ar9002_hw_init_mode_regs(struct ath_hw *ah) in ar9002_hw_init_mode_regs() argument
28 if (AR_SREV_9271(ah)) { in ar9002_hw_init_mode_regs()
29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271); in ar9002_hw_init_mode_regs()
30 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271); in ar9002_hw_init_mode_regs()
31 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg); in ar9002_hw_init_mode_regs()
35 INIT_INI_ARRAY(&ah->iniPcieSerdes, in ar9002_hw_init_mode_regs()
38 if (AR_SREV_9287_11_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
39 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1); in ar9002_hw_init_mode_regs()
40 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1); in ar9002_hw_init_mode_regs()
41 } else if (AR_SREV_9285_12_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
[all …]
Dar9002_calib.c29 static bool ar9002_hw_is_cal_supported(struct ath_hw *ah, in ar9002_hw_is_cal_supported() argument
34 switch (ah->supp_cals & cal_type) { in ar9002_hw_is_cal_supported()
41 if (!((IS_CHAN_2GHZ(chan) || IS_CHAN_A_FAST_CLOCK(ah, chan)) && in ar9002_hw_is_cal_supported()
49 static void ar9002_hw_setup_calibration(struct ath_hw *ah, in ar9002_hw_setup_calibration() argument
52 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_setup_calibration()
54 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
60 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9002_hw_setup_calibration()
65 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); in ar9002_hw_setup_calibration()
69 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); in ar9002_hw_setup_calibration()
74 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
[all …]
Dar9003_mci.c23 static void ar9003_mci_reset_req_wakeup(struct ath_hw *ah) in ar9003_mci_reset_req_wakeup() argument
25 REG_RMW_FIELD(ah, AR_MCI_COMMAND2, in ar9003_mci_reset_req_wakeup()
28 REG_RMW_FIELD(ah, AR_MCI_COMMAND2, in ar9003_mci_reset_req_wakeup()
32 static int ar9003_mci_wait_for_interrupt(struct ath_hw *ah, u32 address, in ar9003_mci_wait_for_interrupt() argument
35 struct ath_common *common = ath9k_hw_common(ah); in ar9003_mci_wait_for_interrupt()
38 if (!(REG_READ(ah, address) & bit_position)) { in ar9003_mci_wait_for_interrupt()
47 REG_WRITE(ah, address, bit_position); in ar9003_mci_wait_for_interrupt()
53 ar9003_mci_reset_req_wakeup(ah); in ar9003_mci_wait_for_interrupt()
57 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, in ar9003_mci_wait_for_interrupt()
60 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_RX_MSG); in ar9003_mci_wait_for_interrupt()
[all …]
Dar9003_phy.c68 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar9003_hw_set_channel() argument
75 ath9k_hw_get_channel_centers(ah, chan, &centers); in ar9003_hw_set_channel()
79 if (AR_SREV_9330(ah)) { in ar9003_hw_set_channel()
80 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
88 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ar9003_hw_set_channel()
98 } else if (AR_SREV_9340(ah)) { in ar9003_hw_set_channel()
99 if (ah->is_clk_25mhz) { in ar9003_hw_set_channel()
106 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) { in ar9003_hw_set_channel()
107 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
121 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) && in ar9003_hw_set_channel()
[all …]
Dani.c107 static void ath9k_hw_update_mibstats(struct ath_hw *ah, in ath9k_hw_update_mibstats() argument
110 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); in ath9k_hw_update_mibstats()
111 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL); in ath9k_hw_update_mibstats()
112 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL); in ath9k_hw_update_mibstats()
113 stats->rts_good += REG_READ(ah, AR_RTS_OK); in ath9k_hw_update_mibstats()
114 stats->beacons += REG_READ(ah, AR_BEACON_CNT); in ath9k_hw_update_mibstats()
117 static void ath9k_ani_restart(struct ath_hw *ah) in ath9k_ani_restart() argument
121 if (!ah->curchan) in ath9k_ani_restart()
124 aniState = &ah->ani; in ath9k_ani_restart()
127 ENABLE_REGWRITE_BUFFER(ah); in ath9k_ani_restart()
[all …]
Dar5008_phy.c49 static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt) in ar5008_write_bank6() argument
51 struct ar5416IniArray *array = &ah->iniBank6; in ar5008_write_bank6()
52 u32 *data = ah->analogBank6Data; in ar5008_write_bank6()
55 ENABLE_REGWRITE_BUFFER(ah); in ar5008_write_bank6()
58 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); in ar5008_write_bank6()
62 REGWRITE_BUFFER_FLUSH(ah); in ar5008_write_bank6()
129 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq) in ar5008_hw_force_bias() argument
131 struct ath_common *common = ath9k_hw_common(ah); in ar5008_hw_force_bias()
136 if (!AR_SREV_5416(ah) || synth_freq >= 3000) in ar5008_hw_force_bias()
139 BUG_ON(AR_SREV_9280_20_OR_LATER(ah)); in ar5008_hw_force_bias()
[all …]
Dar9003_calib.c38 static void ar9003_hw_setup_calibration(struct ath_hw *ah, in ar9003_hw_setup_calibration() argument
41 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_setup_calibration()
50 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_setup_calibration()
53 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9003_hw_setup_calibration()
59 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); in ar9003_hw_setup_calibration()
72 static bool ar9003_hw_per_calibration(struct ath_hw *ah, in ar9003_hw_per_calibration() argument
77 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9003_hw_per_calibration()
84 if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { in ar9003_hw_per_calibration()
88 currCal->calData->calCollect(ah); in ar9003_hw_per_calibration()
89 ah->cal_samples++; in ar9003_hw_per_calibration()
[all …]
Dbtcoex.c55 void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum) in ath9k_hw_init_btcoex_hw() argument
57 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; in ath9k_hw_init_btcoex_hw()
71 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_init_btcoex_hw()
93 void ath9k_hw_btcoex_init_scheme(struct ath_hw *ah) in ath9k_hw_btcoex_init_scheme() argument
95 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_btcoex_init_scheme()
96 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; in ath9k_hw_btcoex_init_scheme()
106 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_btcoex_init_scheme()
111 } else if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_btcoex_init_scheme()
115 if (AR_SREV_9285(ah)) { in ath9k_hw_btcoex_init_scheme()
125 void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah) in ath9k_hw_btcoex_init_2wire() argument
[all …]
Dmac.c21 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, in ath9k_hw_set_txq_interrupts() argument
24 ath_dbg(ath9k_hw_common(ah), INTERRUPT, in ath9k_hw_set_txq_interrupts()
26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, in ath9k_hw_set_txq_interrupts()
27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, in ath9k_hw_set_txq_interrupts()
28 ah->txurn_interrupt_mask); in ath9k_hw_set_txq_interrupts()
30 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_txq_interrupts()
32 REG_WRITE(ah, AR_IMR_S0, in ath9k_hw_set_txq_interrupts()
33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) in ath9k_hw_set_txq_interrupts()
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); in ath9k_hw_set_txq_interrupts()
35 REG_WRITE(ah, AR_IMR_S1, in ath9k_hw_set_txq_interrupts()
[all …]
Dar9003_rtt.c38 void ar9003_hw_rtt_enable(struct ath_hw *ah) in ar9003_hw_rtt_enable() argument
40 REG_WRITE(ah, AR_PHY_RTT_CTRL, 1); in ar9003_hw_rtt_enable()
43 void ar9003_hw_rtt_disable(struct ath_hw *ah) in ar9003_hw_rtt_disable() argument
45 REG_WRITE(ah, AR_PHY_RTT_CTRL, 0); in ar9003_hw_rtt_disable()
48 void ar9003_hw_rtt_set_mask(struct ath_hw *ah, u32 rtt_mask) in ar9003_hw_rtt_set_mask() argument
50 REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL, in ar9003_hw_rtt_set_mask()
54 bool ar9003_hw_rtt_force_restore(struct ath_hw *ah) in ar9003_hw_rtt_force_restore() argument
56 if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL, in ar9003_hw_rtt_force_restore()
61 REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL, in ar9003_hw_rtt_force_restore()
64 if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL, in ar9003_hw_rtt_force_restore()
[all …]
Dar9002_phy.c66 static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar9002_hw_set_channel() argument
73 ath9k_hw_get_channel_centers(ah, chan, &centers); in ar9002_hw_set_channel()
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
88 if (AR_SREV_9287_11_OR_LATER(ah)) { in ar9002_hw_set_channel()
91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484, in ar9002_hw_set_channel()
94 REG_WRITE_ARRAY(&ah->iniCckfirNormal, in ar9002_hw_set_channel()
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar9002_hw_set_channel()
101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { in ar9002_hw_set_channel()
[all …]
Dcalib.c47 static struct ath_nf_limits *ath9k_hw_get_nf_limits(struct ath_hw *ah, in ath9k_hw_get_nf_limits() argument
53 limit = &ah->nf_2g; in ath9k_hw_get_nf_limits()
55 limit = &ah->nf_5g; in ath9k_hw_get_nf_limits()
60 static s16 ath9k_hw_get_default_nf(struct ath_hw *ah, in ath9k_hw_get_default_nf() argument
63 return ath9k_hw_get_nf_limits(ah, chan)->nominal; in ath9k_hw_get_default_nf()
66 s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_getchan_noise() argument
73 ath9k_hw_get_default_nf(ah, chan); in ath9k_hw_getchan_noise()
81 static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah, in ath9k_hw_update_nfcal_hist_buffer() argument
85 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_update_nfcal_hist_buffer()
89 u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask; in ath9k_hw_update_nfcal_hist_buffer()
[all …]
/drivers/net/wireless/ath/ath5k/
Dattach.c35 static int ath5k_hw_post(struct ath5k_hw *ah) in ath5k_hw_post() argument
54 init_val = ath5k_hw_reg_read(ah, cur_reg); in ath5k_hw_post()
58 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
59 cur_val = ath5k_hw_reg_read(ah, cur_reg); in ath5k_hw_post()
62 ATH5K_ERR(ah, "POST Failed !!!\n"); in ath5k_hw_post()
68 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
73 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
74 cur_val = ath5k_hw_reg_read(ah, cur_reg); in ath5k_hw_post()
77 ATH5K_ERR(ah, "POST Failed !!!\n"); in ath5k_hw_post()
83 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
[all …]
Dbase.c97 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
187 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) in ath5k_extend_tsf() argument
189 u64 tsf = ath5k_hw_get_tsf64(ah); in ath5k_extend_tsf()
220 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; in ath5k_ioread32() local
221 return ath5k_hw_reg_read(ah, reg_offset); in ath5k_ioread32()
226 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; in ath5k_iowrite32() local
227 ath5k_hw_reg_write(ah, val, reg_offset); in ath5k_iowrite32()
243 struct ath5k_hw *ah = hw->priv; in ath5k_reg_notifier() local
244 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); in ath5k_reg_notifier()
282 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, in ath5k_setup_channels() argument
[all …]
Dreset.c67 ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, in ath5k_hw_register_timeout() argument
74 data = ath5k_hw_reg_read(ah, reg); in ath5k_hw_register_timeout()
101 ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec) in ath5k_hw_htoclock() argument
103 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_htoclock()
118 ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock) in ath5k_hw_clocktoh() argument
120 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_clocktoh()
132 ath5k_hw_init_core_clock(struct ath5k_hw *ah) in ath5k_hw_init_core_clock() argument
134 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_init_core_clock()
135 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_init_core_clock()
156 switch (ah->ah_bwmode) { in ath5k_hw_init_core_clock()
[all …]
Dani.c66 ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level) in ath5k_ani_set_noise_immunity_level() argument
86 ATH5K_ERR(ah, "noise immunity level %d out of range", in ath5k_ani_set_noise_immunity_level()
91 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, in ath5k_ani_set_noise_immunity_level()
93 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE, in ath5k_ani_set_noise_immunity_level()
95 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE, in ath5k_ani_set_noise_immunity_level()
97 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG, in ath5k_ani_set_noise_immunity_level()
100 ah->ani_state.noise_imm_level = level; in ath5k_ani_set_noise_immunity_level()
101 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level); in ath5k_ani_set_noise_immunity_level()
111 ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level) in ath5k_ani_set_spur_immunity_level() argument
116 level > ah->ani_state.max_spur_level) { in ath5k_ani_set_spur_immunity_level()
[all …]
Dpcu.c113 ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum ieee80211_band band, in ath5k_hw_get_frame_duration() argument
121 if (!ah->ah_bwmode) { in ath5k_hw_get_frame_duration()
122 __le16 raw_dur = ieee80211_generic_frame_duration(ah->hw, in ath5k_hw_get_frame_duration()
138 switch (ah->ah_bwmode) { in ath5k_hw_get_frame_duration()
175 ath5k_hw_get_default_slottime(struct ath5k_hw *ah) in ath5k_hw_get_default_slottime() argument
177 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_get_default_slottime()
180 switch (ah->ah_bwmode) { in ath5k_hw_get_default_slottime()
193 if ((channel->hw_value == AR5K_MODE_11B) && !ah->ah_short_slot) in ath5k_hw_get_default_slottime()
206 ath5k_hw_get_default_sifs(struct ath5k_hw *ah) in ath5k_hw_get_default_sifs() argument
208 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_get_default_sifs()
[all …]
Dqcu.c63 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) in ath5k_hw_num_tx_pending() argument
66 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); in ath5k_hw_num_tx_pending()
69 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) in ath5k_hw_num_tx_pending()
73 if (ah->ah_version == AR5K_AR5210) in ath5k_hw_num_tx_pending()
76 pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue)); in ath5k_hw_num_tx_pending()
82 if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) in ath5k_hw_num_tx_pending()
94 ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue) in ath5k_hw_release_tx_queue() argument
96 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num)) in ath5k_hw_release_tx_queue()
100 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE; in ath5k_hw_release_tx_queue()
102 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue); in ath5k_hw_release_tx_queue()
[all …]
Dphy.c84 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band) in ath5k_hw_radio_revision() argument
95 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
98 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
107 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); in ath5k_hw_radio_revision()
110 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); in ath5k_hw_radio_revision()
112 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_radio_revision()
113 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(256)) >> 28) & 0xf; in ath5k_hw_radio_revision()
116 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; in ath5k_hw_radio_revision()
122 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
136 ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel) in ath5k_channel_ok() argument
[all …]
Ddma.c48 ath5k_hw_start_rx_dma(struct ath5k_hw *ah) in ath5k_hw_start_rx_dma() argument
50 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR); in ath5k_hw_start_rx_dma()
51 ath5k_hw_reg_read(ah, AR5K_CR); in ath5k_hw_start_rx_dma()
59 ath5k_hw_stop_rx_dma(struct ath5k_hw *ah) in ath5k_hw_stop_rx_dma() argument
63 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR); in ath5k_hw_stop_rx_dma()
69 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0; in ath5k_hw_stop_rx_dma()
74 ATH5K_DBG(ah, ATH5K_DEBUG_DMA, in ath5k_hw_stop_rx_dma()
85 ath5k_hw_get_rxdp(struct ath5k_hw *ah) in ath5k_hw_get_rxdp() argument
87 return ath5k_hw_reg_read(ah, AR5K_RXDP); in ath5k_hw_get_rxdp()
98 ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr) in ath5k_hw_set_rxdp() argument
[all …]
Dmac80211-ops.c61 struct ath5k_hw *ah = hw->priv; in ath5k_tx() local
64 if (WARN_ON(qnum >= ah->ah_capabilities.cap_queues.q_tx_num)) { in ath5k_tx()
69 ath5k_tx_queue(hw, skb, &ah->txqs[qnum], control); in ath5k_tx()
76 struct ath5k_hw *ah = hw->priv; in ath5k_add_interface() local
80 mutex_lock(&ah->lock); in ath5k_add_interface()
84 && (ah->num_ap_vifs + ah->num_adhoc_vifs) >= ATH_BCBUF) { in ath5k_add_interface()
94 if (ah->num_adhoc_vifs || in ath5k_add_interface()
95 (ah->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) { in ath5k_add_interface()
96 ATH5K_ERR(ah, "Only one single ad-hoc interface is allowed.\n"); in ath5k_add_interface()
113 ah->nvifs++; in ath5k_add_interface()
[all …]
Drfkill.c39 static inline void ath5k_rfkill_disable(struct ath5k_hw *ah) in ath5k_rfkill_disable() argument
41 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "rfkill disable (gpio:%d polarity:%d)\n", in ath5k_rfkill_disable()
42 ah->rf_kill.gpio, ah->rf_kill.polarity); in ath5k_rfkill_disable()
43 ath5k_hw_set_gpio_output(ah, ah->rf_kill.gpio); in ath5k_rfkill_disable()
44 ath5k_hw_set_gpio(ah, ah->rf_kill.gpio, !ah->rf_kill.polarity); in ath5k_rfkill_disable()
48 static inline void ath5k_rfkill_enable(struct ath5k_hw *ah) in ath5k_rfkill_enable() argument
50 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "rfkill enable (gpio:%d polarity:%d)\n", in ath5k_rfkill_enable()
51 ah->rf_kill.gpio, ah->rf_kill.polarity); in ath5k_rfkill_enable()
52 ath5k_hw_set_gpio_output(ah, ah->rf_kill.gpio); in ath5k_rfkill_enable()
53 ath5k_hw_set_gpio(ah, ah->rf_kill.gpio, ah->rf_kill.polarity); in ath5k_rfkill_enable()
[all …]

1234567