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Searched refs:PACKET0 (Results 1 – 25 of 35) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
Duvd_v6_0.c175 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init()
179 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init()
183 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v6_0_hw_init()
188 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v6_0_hw_init()
191 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()
560 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v6_0_ring_emit_fence()
562 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_fence()
564 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v6_0_ring_emit_fence()
566 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v6_0_ring_emit_fence()
569 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v6_0_ring_emit_fence()
[all …]
Duvd_v4_2.c173 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init()
177 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init()
181 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v4_2_hw_init()
186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v4_2_hw_init()
189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init()
449 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_emit_fence()
451 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v4_2_ring_emit_fence()
453 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v4_2_ring_emit_fence()
455 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v4_2_ring_emit_fence()
458 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v4_2_ring_emit_fence()
[all …]
Duvd_v5_0.c168 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v5_0_hw_init()
172 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v5_0_hw_init()
176 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v5_0_hw_init()
181 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v5_0_hw_init()
184 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init()
464 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_emit_fence()
466 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v5_0_ring_emit_fence()
468 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); in uvd_v5_0_ring_emit_fence()
470 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); in uvd_v5_0_ring_emit_fence()
473 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); in uvd_v5_0_ring_emit_fence()
[all …]
Dvcn_v1_0.c770 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_insert_start()
773 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_insert_start()
787 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_insert_end()
805 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); in vcn_v1_0_dec_ring_emit_fence()
808 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_emit_fence()
811 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_fence()
814 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_emit_fence()
818 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in vcn_v1_0_dec_ring_emit_fence()
821 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in vcn_v1_0_dec_ring_emit_fence()
824 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in vcn_v1_0_dec_ring_emit_fence()
[all …]
Duvd_v7_0.c518 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0, in uvd_v7_0_hw_init()
523 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0, in uvd_v7_0_hw_init()
528 tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0, in uvd_v7_0_hw_init()
534 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, in uvd_v7_0_hw_init()
538 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, in uvd_v7_0_hw_init()
1098 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); in uvd_v7_0_ring_emit_fence()
1101 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_fence()
1104 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); in uvd_v7_0_ring_emit_fence()
1107 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); in uvd_v7_0_ring_emit_fence()
1111 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); in uvd_v7_0_ring_emit_fence()
[all …]
Damdgpu_uvd.c990 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0); in amdgpu_uvd_send_msg()
991 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0); in amdgpu_uvd_send_msg()
992 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0); in amdgpu_uvd_send_msg()
993 data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0); in amdgpu_uvd_send_msg()
995 data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); in amdgpu_uvd_send_msg()
996 data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); in amdgpu_uvd_send_msg()
997 data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); in amdgpu_uvd_send_msg()
998 data[3] = PACKET0(mmUVD_NO_OP, 0); in amdgpu_uvd_send_msg()
Damdgpu_vcn.c257 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); in amdgpu_vcn_dec_ring_test_ring()
311 ib->ptr[0] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0); in amdgpu_vcn_dec_send_msg()
313 ib->ptr[2] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0); in amdgpu_vcn_dec_send_msg()
315 ib->ptr[4] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0); in amdgpu_vcn_dec_send_msg()
318 ib->ptr[i] = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0); in amdgpu_vcn_dec_send_msg()
Dsoc15d.h41 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ macro
Dvid.h96 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ macro
Dcikd.h216 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ macro
/drivers/gpu/drm/radeon/
Duvd_v2_2.c45 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0)); in uvd_v2_2_fence_emit()
47 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit()
49 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit()
51 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v2_2_fence_emit()
54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v2_2_fence_emit()
56 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v2_2_fence_emit()
58 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v2_2_fence_emit()
79 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in uvd_v2_2_semaphore_emit()
82 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in uvd_v2_2_semaphore_emit()
85 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in uvd_v2_2_semaphore_emit()
Duvd_v1_0.c87 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v1_0_fence_emit()
89 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v1_0_fence_emit()
91 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v1_0_fence_emit()
94 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0)); in uvd_v1_0_fence_emit()
96 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0)); in uvd_v1_0_fence_emit()
98 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0)); in uvd_v1_0_fence_emit()
186 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); in uvd_v1_0_init()
190 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v1_0_init()
194 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); in uvd_v1_0_init()
199 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0)); in uvd_v1_0_init()
[all …]
Dr300.c216 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); in r300_fence_ring_emit()
218 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); in r300_fence_ring_emit()
221 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r300_fence_ring_emit()
223 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); in r300_fence_ring_emit()
226 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r300_fence_ring_emit()
230 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r300_fence_ring_emit()
233 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r300_fence_ring_emit()
236 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r300_fence_ring_emit()
238 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); in r300_fence_ring_emit()
269 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); in r300_ring_start()
[all …]
Duvd_v3_1.c47 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0)); in uvd_v3_1_semaphore_emit()
50 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0)); in uvd_v3_1_semaphore_emit()
53 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0)); in uvd_v3_1_semaphore_emit()
Drv515.c70 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)); in rv515_ring_start()
76 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
78 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); in rv515_ring_start()
80 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)); in rv515_ring_start()
82 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)); in rv515_ring_start()
84 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)); in rv515_ring_start()
86 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)); in rv515_ring_start()
88 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); in rv515_ring_start()
90 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); in rv515_ring_start()
92 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)); in rv515_ring_start()
[all …]
Dr200.c105 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma()
113 radeon_ring_write(ring, PACKET0(0x720, 2)); in r200_copy_dma()
120 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r200_copy_dma()
Dradeon_uvd.c751 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0); in radeon_uvd_send_msg()
753 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0); in radeon_uvd_send_msg()
755 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0); in radeon_uvd_send_msg()
758 ib.ptr[i] = PACKET0(UVD_NO_OP, 0); in radeon_uvd_send_msg()
Dr420.c218 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); in r420_cp_errata_init()
234 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); in r420_cp_errata_fini()
Dr100.c843 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r100_ring_hdp_flush()
846 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); in r100_ring_hdp_flush()
859 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); in r100_fence_ring_emit()
861 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); in r100_fence_ring_emit()
864 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r100_fence_ring_emit()
868 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); in r100_fence_ring_emit()
870 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); in r100_fence_ring_emit()
945 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); in r100_copy_blit()
947 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); in r100_copy_blit()
984 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); in r100_ring_start()
[all …]
Dr300d.h60 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
Dni.c2055 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in cayman_uvd_resume()
2692 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); in cayman_vm_flush()
2696 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); in cayman_vm_flush()
2700 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); in cayman_vm_flush()
Drv515d.h200 #define PACKET0(reg, n) (CP_PACKET0 | \ macro
Drv770d.h985 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
Dnid.h1148 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ macro
Dr100d.h59 #define PACKET0(reg, n) (CP_PACKET0 | \ macro

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