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Searched refs:mclk_table (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/powerplay/hwmgr/
Dsmu7_hwmgr.c632 &data->dpm_table.mclk_table, in smu7_reset_dpm_tables()
700 data->dpm_table.mclk_table.count = 0; in smu7_setup_dpm_tables_v0()
702 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
704 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v0()
706 …data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 … in smu7_setup_dpm_tables_v0()
707 data->dpm_table.mclk_table.count++; in smu7_setup_dpm_tables_v0()
794 data->dpm_table.mclk_table.count = 0; in smu7_setup_dpm_tables_v1()
796 if (i == 0 || data->dpm_table.mclk_table.dpm_levels in smu7_setup_dpm_tables_v1()
797 [data->dpm_table.mclk_table.count - 1].value != in smu7_setup_dpm_tables_v1()
799 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v1()
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Dvega10_processpptables.c568 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
577 mclk_table = (phm_ppt_v1_clock_voltage_dependency_table *) in get_mclk_voltage_dependency_table()
580 if (!mclk_table) in get_mclk_voltage_dependency_table()
583 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
586 mclk_table->entries[i].vddInd = in get_mclk_voltage_dependency_table()
588 mclk_table->entries[i].vddciInd = in get_mclk_voltage_dependency_table()
590 mclk_table->entries[i].mvddInd = in get_mclk_voltage_dependency_table()
592 mclk_table->entries[i].clk = in get_mclk_voltage_dependency_table()
596 *pp_vega10_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
Dprocess_pptables_v1_0.c378 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
388 mclk_table = kzalloc(table_size, GFP_KERNEL); in get_mclk_voltage_dependency_table()
390 if (NULL == mclk_table) in get_mclk_voltage_dependency_table()
393 memset(mclk_table, 0x00, table_size); in get_mclk_voltage_dependency_table()
395 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
400 entries, mclk_table, i); in get_mclk_voltage_dependency_table()
411 *pp_tonga_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
Dvega10_hwmgr.c610 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = in vega10_patch_voltage_dependency_tables_with_lookup_table() local
651 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { in vega10_patch_voltage_dependency_tables_with_lookup_table()
652 voltage_id = mclk_table->entries[entry_id].vddInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
653 mclk_table->entries[entry_id].vddc = in vega10_patch_voltage_dependency_tables_with_lookup_table()
655 voltage_id = mclk_table->entries[entry_id].vddciInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
656 mclk_table->entries[entry_id].vddci = in vega10_patch_voltage_dependency_tables_with_lookup_table()
658 voltage_id = mclk_table->entries[entry_id].mvddInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
659 mclk_table->entries[entry_id].mvdd = in vega10_patch_voltage_dependency_tables_with_lookup_table()
3321 struct vega10_single_dpm_table *mclk_table = in vega10_find_dpm_states_clocks_in_dpm_table() local
3380 for (i = 0; i < mclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
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Dsmu7_hwmgr.h110 struct smu7_single_dpm_table mclk_table; member
/drivers/gpu/drm/amd/amdgpu/
Dci_dpm.c2684 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2687 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
3471 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
3472 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3475 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3481 if ((dpm_table->mclk_table.count >= 2) && in ci_populate_all_memory_levels()
3491 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3493 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
3495 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3600 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
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Dci_dpm.h70 struct ci_single_dpm_table mclk_table; member
/drivers/gpu/drm/amd/powerplay/smumgr/
Diceland_smc.c1233 for (i = 0; i < dpm_table->mclk_table.count; i++) { in iceland_populate_all_memory_levels()
1234 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in iceland_populate_all_memory_levels()
1236 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in iceland_populate_all_memory_levels()
1254 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in iceland_populate_all_memory_levels()
1255 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in iceland_populate_all_memory_levels()
1257 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in iceland_populate_all_memory_levels()
1507 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in iceland_program_memory_timing_parameters()
1510 data->dpm_table.mclk_table.dpm_levels[j].value, in iceland_program_memory_timing_parameters()
1553 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in iceland_populate_smc_boot_level()
1649 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in iceland_convert_mc_reg_table_to_smc()
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Dfiji_smc.c1015 for (i = 0; i < dpm_table->mclk_table.count; i++) { in fiji_populate_all_memory_levels()
1016 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in fiji_populate_all_memory_levels()
1020 dpm_table->mclk_table.dpm_levels[i].value, in fiji_populate_all_memory_levels()
1038 (uint8_t)dpm_table->mclk_table.count; in fiji_populate_all_memory_levels()
1040 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in fiji_populate_all_memory_levels()
1042 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = in fiji_populate_all_memory_levels()
1163 data->dpm_table.mclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1184 data->dpm_table.mclk_table.dpm_levels[0].value, in fiji_populate_smc_acpi_level()
1361 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in fiji_program_memory_timing_parameters()
1364 data->dpm_table.mclk_table.dpm_levels[j].value, in fiji_program_memory_timing_parameters()
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Dpolaris10_smc.c917 for (i = 0; i < dpm_table->mclk_table.count; i++) { in polaris10_populate_all_memory_levels()
918 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in polaris10_populate_all_memory_levels()
922 dpm_table->mclk_table.dpm_levels[i].value, in polaris10_populate_all_memory_levels()
924 if (i == dpm_table->mclk_table.count - 1) { in polaris10_populate_all_memory_levels()
941 (uint8_t)dpm_table->mclk_table.count; in polaris10_populate_all_memory_levels()
943 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in polaris10_populate_all_memory_levels()
1051 data->dpm_table.mclk_table.dpm_levels[0].value, in polaris10_populate_smc_acpi_level()
1212 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in polaris10_program_memory_timing_parameters()
1215 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in polaris10_program_memory_timing_parameters()
1218 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j); in polaris10_program_memory_timing_parameters()
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Dtonga_smc.c1022 for (i = 0; i < dpm_table->mclk_table.count; i++) { in tonga_populate_all_memory_levels()
1023 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in tonga_populate_all_memory_levels()
1028 dpm_table->mclk_table.dpm_levels[i].value, in tonga_populate_all_memory_levels()
1045 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in tonga_populate_all_memory_levels()
1046 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in tonga_populate_all_memory_levels()
1048 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in tonga_populate_all_memory_levels()
1465 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in tonga_program_memory_timing_parameters()
1468 data->dpm_table.mclk_table.dpm_levels[j].value, in tonga_program_memory_timing_parameters()
1512 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in tonga_populate_smc_boot_level()
2140 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in tonga_convert_mc_reg_table_to_smc()
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/drivers/gpu/drm/radeon/
Dci_dpm.c2532 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2535 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
3312 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
3313 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3316 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3324 if ((dpm_table->mclk_table.count >= 2) && in ci_populate_all_memory_levels()
3334 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3336 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
3338 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3443 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
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Dci_dpm.h69 struct ci_single_dpm_table mclk_table; member