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Searched refs:readw (Results 1 – 25 of 253) sorted by relevance

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/drivers/scsi/qla4xxx/
Dql4_dbg.c47 readw(&ha->reg->mailbox[i])); in qla4xxx_dump_registers()
52 readw(&ha->reg->flash_address)); in qla4xxx_dump_registers()
55 readw(&ha->reg->flash_data)); in qla4xxx_dump_registers()
58 readw(&ha->reg->ctrl_status)); in qla4xxx_dump_registers()
63 readw(&ha->reg->u1.isp4010.nvram)); in qla4xxx_dump_registers()
67 readw(&ha->reg->u1.isp4022.intr_mask)); in qla4xxx_dump_registers()
70 readw(&ha->reg->u1.isp4022.nvram)); in qla4xxx_dump_registers()
73 readw(&ha->reg->u1.isp4022.semaphore)); in qla4xxx_dump_registers()
77 readw(&ha->reg->req_q_in)); in qla4xxx_dump_registers()
80 readw(&ha->reg->rsp_q_out)); in qla4xxx_dump_registers()
[all …]
/drivers/scsi/arm/
Dcumana_1.c129 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
130 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
131 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
132 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
133 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
134 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
135 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
136 *laddr++ = readw(dma) | (readw(dma) << 16); in cumanascsi_pread()
/drivers/net/ethernet/stmicro/stmmac/
Daltr_tse_pcs.c82 val = readw(base + TSE_PCS_CONTROL_REG); in tse_pcs_reset()
87 val = readw(base + TSE_PCS_CONTROL_REG); in tse_pcs_reset()
128 val = readw(tse_pcs_base + TSE_PCS_STATUS_REG); in pcs_link_timer_callback()
150 val = readw(tse_pcs_base + TSE_PCS_STATUS_REG); in auto_nego_timer_callback()
155 val = readw(tse_pcs_base + TSE_PCS_PARTNER_ABILITY_REG); in auto_nego_timer_callback()
194 val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); in auto_nego_timer_callback()
227 val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); in tse_pcs_fix_mac_speed()
231 val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG); in tse_pcs_fix_mac_speed()
235 val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); in tse_pcs_fix_mac_speed()
245 val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG); in tse_pcs_fix_mac_speed()
[all …]
/drivers/watchdog/
Dcoh901327_wdt.c87 val = readw(virtbase + U300_WDOG_D2R); in coh901327_enable()
111 (void) readw(virtbase + U300_WDOG_CR); in coh901327_enable()
112 val = readw(virtbase + U300_WDOG_D2R); in coh901327_enable()
126 val = readw(virtbase + U300_WDOG_D2R); in coh901327_disable()
136 val = readw(virtbase + U300_WDOG_D2R); in coh901327_disable()
180 val = readw(virtbase + U300_WDOG_CR); in coh901327_gettimeleft()
182 val = readw(virtbase + U300_WDOG_CR); in coh901327_gettimeleft()
207 val = readw(virtbase + U300_WDOG_IER); in coh901327_interrupt()
278 val = readw(virtbase + U300_WDOG_SR); in coh901327_probe()
293 val = readw(virtbase + U300_WDOG_D2R); in coh901327_probe()
[all …]
/drivers/input/keyboard/
Dimx_keypad.c97 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
101 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
107 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
116 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
130 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
138 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
262 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
266 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
280 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
284 reg_val = readw(keypad->mmio_base + KPSR); in imx_keypad_check_for_events()
[all …]
/drivers/tty/
Dmoxa.c242 while (readw(ofsAddr + FuncCode) != 0) in moxa_wait_finish()
245 if (readw(ofsAddr + FuncCode) != 0) in moxa_wait_finish()
267 ret = readw(ofsAddr + FuncArg); in moxafuncret()
277 rptr = readw(ofsAddr + RXrptr); in moxa_low_water_check()
278 wptr = readw(ofsAddr + RXwptr); in moxa_low_water_check()
279 mask = readw(ofsAddr + RX_mask); in moxa_low_water_check()
486 tmp = readw(baseAddr + C218_key); in moxa_load_bios()
491 tmp = readw(baseAddr + C218_key); in moxa_load_bios()
496 tmp = readw(baseAddr + C320_key); in moxa_load_bios()
499 tmp = readw(baseAddr + C320_status); in moxa_load_bios()
[all …]
/drivers/i2c/busses/
Di2c-wmt.c102 while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) { in wmt_i2c_wait_bus_not_busy()
153 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write()
157 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write()
174 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write()
192 val = readw(i2c_dev->base + REG_CSR); in wmt_i2c_write()
232 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
236 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
241 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
247 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
264 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_read()
[all …]
/drivers/media/pci/netup_unidvb/
Dnetup_unidvb_i2c.c81 reg = readw(&i2c->regs->twi_ctrl0_stat); in netup_i2c_interrupt()
104 tmp = readw(&i2c->regs->rx_fifo.stat_ctrl); in netup_i2c_interrupt()
112 tmp = readw(&i2c->regs->tx_fifo.stat_ctrl); in netup_i2c_interrupt()
144 (readw(&i2c->regs->tx_fifo.stat_ctrl) & 0x3f); in netup_i2c_fifo_tx()
157 writew(readw(&i2c->regs->tx_fifo.stat_ctrl) | FIFO_IRQEN, in netup_i2c_fifo_tx()
165 u32 fifo_size = readw(&i2c->regs->rx_fifo.stat_ctrl) & 0x3f; in netup_i2c_fifo_rx()
181 writew(readw(&i2c->regs->rx_fifo.stat_ctrl) | FIFO_IRQEN, in netup_i2c_fifo_rx()
189 u16 reg = readw(&i2c->regs->twi_ctrl0_stat); in netup_i2c_start_xfer()
197 __func__, readw(&i2c->regs->length), in netup_i2c_start_xfer()
198 readw(&i2c->regs->twi_addr_ctrl1), in netup_i2c_start_xfer()
[all …]
Dnetup_unidvb_ci.c69 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_ts_ctl()
75 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_ts_ctl()
100 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_reset()
108 ci_stat = readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET); in netup_unidvb_ci_slot_reset()
132 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_poll_ci_slot_status()
133 ci_stat = readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET); in netup_unidvb_poll_ci_slot_status()
Dnetup_unidvb_spi.c87 reg = readw(&spi->regs->control_stat); in netup_spi_interrupt()
95 reg = readw(&spi->regs->control_stat); in netup_spi_interrupt()
145 __func__, readw(&spi->regs->control_stat)); in netup_spi_transfer()
239 reg = readw(&spi->regs->control_stat); in netup_spi_release()
241 reg = readw(&spi->regs->control_stat); in netup_spi_release()
/drivers/net/can/
Dbfin_can.c212 while (!(readw(&reg->control) & CCA)) { in bfin_can_set_reset_mode()
265 writew(readw(&reg->control) & ~CCR, &reg->control); in bfin_can_set_normal_mode()
267 while (readw(&reg->status) & CCA) { in bfin_can_set_normal_mode()
333 u16 cec = readw(&reg->cec); in bfin_can_get_berr_counter()
403 cf->can_id = ((readw(&reg->chl[RECEIVE_EXT_CHL].id1) in bfin_can_rx()
405 + readw(&reg->chl[RECEIVE_EXT_CHL].id0); in bfin_can_rx()
410 cf->can_id = (readw(&reg->chl[RECEIVE_STD_CHL].id1) in bfin_can_rx()
414 if (readw(&reg->chl[obj].id1) & RTR) in bfin_can_rx()
418 cf->can_dlc = get_can_dlc(readw(&reg->chl[obj].dlc) & 0xF); in bfin_can_rx()
422 val = readw(&reg->chl[obj].data[i]); in bfin_can_rx()
[all …]
/drivers/rtc/
Drtc-mxc.c119 day = readw(ioaddr + RTC_DAYR); in get_alarm_or_time()
120 hr_min = readw(ioaddr + RTC_HOURMIN); in get_alarm_or_time()
121 sec = readw(ioaddr + RTC_SECOND); in get_alarm_or_time()
124 day = readw(ioaddr + RTC_DAYALARM); in get_alarm_or_time()
125 hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff; in get_alarm_or_time()
126 sec = readw(ioaddr + RTC_ALRM_SEC); in get_alarm_or_time()
186 writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR); in rtc_update_alarm()
199 reg = readw(ioaddr + RTC_RTCIENR); in mxc_rtc_irq_enable()
221 status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR); in mxc_rtc_interrupt()
303 alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0; in mxc_rtc_read_alarm()
[all …]
Drtc-s3c.c409 con = readw(info->base + S3C2410_RTCCON); in s3c24xx_rtc_enable()
414 tmp = readw(info->base + S3C2410_RTCCON); in s3c24xx_rtc_enable()
421 tmp = readw(info->base + S3C2410_RTCCON); in s3c24xx_rtc_enable()
429 tmp = readw(info->base + S3C2410_RTCCON); in s3c24xx_rtc_enable()
439 con = readw(info->base + S3C2410_RTCCON); in s3c24xx_rtc_disable()
452 con = readw(info->base + S3C2410_RTCCON); in s3c6410_rtc_disable()
560 readw(info->base + S3C2410_RTCCON)); in s3c_rtc_probe()
751 con = readw(info->base + S3C2410_RTCCON); in s3c2416_rtc_select_tick_clk()
760 ticnt = readw(info->base + S3C2410_RTCCON); in s3c6410_rtc_enable_tick()
778 info->ticnt_en_save = readw(info->base + S3C2410_RTCCON); in s3c6410_rtc_save_tick_cnt()
[all …]
/drivers/clk/
Dclk-u300.c464 val = readw(sclk->res_reg); in syscon_block_reset_enable()
480 val = readw(sclk->res_reg); in syscon_block_reset_disable()
549 val = readw(sclk->en_reg); in syscon_clk_is_enabled()
559 val = readw(syscon_vbase + U300_SYSCON_CCR); in syscon_get_perf()
675 val |= readw(syscon_vbase + U300_SYSCON_CCR) & in syscon_clk_set_rate()
963 val = readw(syscon_vbase + U300_SYSCON_MMCR); in mclk_clk_prepare()
970 val = readw(syscon_vbase + U300_SYSCON_MMCR); in mclk_clk_prepare()
1013 u16 val = readw(syscon_vbase + U300_SYSCON_MMF0R) & in mclk_clk_recalc_rate()
1104 reg = readw(syscon_vbase + U300_SYSCON_MMF0R) & in mclk_clk_set_rate()
1190 val = readw(syscon_vbase + U300_SYSCON_CCR); in u300_clk_init()
[all …]
/drivers/net/ethernet/packetengines/
Dhamachi.c744 dev->name, readw(ioaddr + MiscStatus) & 1 ? 64 : 32, in hamachi_init_one()
746 readw(ioaddr + ANLinkPartnerAbility)); in hamachi_init_one()
819 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_read()
824 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_read()
826 return readw(ioaddr + MII_Rd_Data); in mdio_read()
837 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_write()
844 if ((readw(ioaddr + MII_Status) & 1) == 0) in mdio_write()
885 fifo_info = (readw(ioaddr + GPIO) & 0x00C0) >> 6; in hamachi_open()
979 dev->name, readw(ioaddr + RxStatus), readw(ioaddr + TxStatus)); in hamachi_open()
1031 "%4.4x.\n", dev->name, readw(ioaddr + ANStatus), in hamachi_timer()
[all …]
/drivers/staging/comedi/drivers/
Ddaqboard2000.c321 status = readw(dev->mmio + DB2K_REG_ACQ_STATUS); in db2k_ai_status()
382 data[i] = readw(dev->mmio + DB2K_REG_ACQ_RESULTS_FIFO); in db2k_ai_insn_read()
398 status = readw(dev->mmio + DB2K_REG_DAC_STATUS); in db2k_ao_eoc()
480 cpld = readw(dev->mmio + DB2K_REG_CPLD_STATUS); in db2k_wait_cpld_init()
496 if (readw(dev->mmio + DB2K_REG_CPLD_STATUS) & in db2k_wait_cpld_txready()
517 if (!(readw(dev->mmio + DB2K_REG_CPLD_STATUS) & DB2K_CPLD_STATUS_INIT)) in db2k_write_cpld()
583 new_cpld = (readw(dev->mmio + DB2K_REG_CPLD_STATUS) & in db2k_load_firmware()
640 val = readw(dev->mmio + DB2K_REG_DAC_STATUS); in db2k_activate_reference_dacs()
650 val = readw(dev->mmio + DB2K_REG_DAC_STATUS); in db2k_activate_reference_dacs()
689 return readw(dev->mmio + iobase + port * 2); in db2k_8255_cb()
Dme_daq.c212 val = readw(mmio_porta); in me_dio_insn_bits()
217 val |= (readw(mmio_portb) << 16); in me_dio_insn_bits()
231 status = readw(dev->mmio + ME_STATUS_REG); in me_ai_eoc()
283 readw(dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
291 val = readw(dev->mmio + ME_AI_FIFO_REG) & s->maxdata; in me_ai_insn_read()
332 readw(dev->mmio + ME_DAC_CTRL_REG); in me_ao_insn_write()
343 readw(dev->mmio + ME_CTRL2_REG); in me_ao_insn_write()
361 value = readw(dev->mmio + XILINX_DOWNLOAD_RESET); in me2600_xilinx_download()
/drivers/pci/
Drom.c94 if (readw(image) != 0xAA55) { in pci_get_rom_size()
96 readw(image)); in pci_get_rom_size()
100 pds = image + readw(image + 24); in pci_get_rom_size()
107 length = readw(pds + 16); in pci_get_rom_size()
/drivers/dma/ioat/
Ddca.c159 readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); in ioat_dca_add_requester()
185 readw(ioatdca->dca_base + IOAT3_DCA_GREQID_OFFSET); in ioat_dca_remove_requester()
240 global_req_table = readw(iobase + dca_offset + IOAT3_DCA_GREQID_OFFSET); in ioat_dca_count_dca_slots()
292 dca_offset = readw(iobase + IOAT_DCAOFFSET_OFFSET); in ioat_dca_init()
312 csi_fsb_control = readw(ioatdca->dca_base + IOAT3_CSI_CONTROL_OFFSET); in ioat_dca_init()
318 pcie_control = readw(ioatdca->dca_base + IOAT3_PCI_CONTROL_OFFSET); in ioat_dca_init()
/drivers/pwm/
Dpwm-tiecap.c91 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_config()
113 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_config()
132 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_set_polarity()
160 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_enable()
176 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_disable()
276 pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2); in ecap_pwm_save_context()
/drivers/usb/musb/
Dsunxi.c195 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX); in sunxi_musb_interrupt()
199 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX); in sunxi_musb_interrupt()
540 return readw(addr + SUNXI_MUSB_INTRTX); in sunxi_musb_readw()
542 return readw(addr + SUNXI_MUSB_INTRRX); in sunxi_musb_readw()
544 return readw(addr + SUNXI_MUSB_INTRTXE); in sunxi_musb_readw()
546 return readw(addr + SUNXI_MUSB_INTRRXE); in sunxi_musb_readw()
548 return readw(addr + SUNXI_MUSB_FRAME); in sunxi_musb_readw()
550 return readw(addr + SUNXI_MUSB_TXFIFOADD); in sunxi_musb_readw()
552 return readw(addr + SUNXI_MUSB_RXFIFOADD); in sunxi_musb_readw()
562 return readw(addr + offset); in sunxi_musb_readw()
[all …]
/drivers/ata/
Dsata_vsc.c205 tf->device = readw(ioaddr->device_addr); in vsc_sata_tf_read()
206 feature = readw(ioaddr->error_addr); in vsc_sata_tf_read()
207 nsect = readw(ioaddr->nsect_addr); in vsc_sata_tf_read()
208 lbal = readw(ioaddr->lbal_addr); in vsc_sata_tf_read()
209 lbam = readw(ioaddr->lbam_addr); in vsc_sata_tf_read()
210 lbah = readw(ioaddr->lbah_addr); in vsc_sata_tf_read()
/drivers/hsi/controllers/
Domap_ssi_core.c94 readw(gdd + SSI_GDD_CSDP_REG(lch))); in ssi_debug_gdd_show()
96 readw(gdd + SSI_GDD_CCR_REG(lch))); in ssi_debug_gdd_show()
98 readw(gdd + SSI_GDD_CICR_REG(lch))); in ssi_debug_gdd_show()
100 readw(gdd + SSI_GDD_CSR_REG(lch))); in ssi_debug_gdd_show()
106 readw(gdd + SSI_GDD_CEN_REG(lch))); in ssi_debug_gdd_show()
108 readw(gdd + SSI_GDD_CSAC_REG(lch))); in ssi_debug_gdd_show()
110 readw(gdd + SSI_GDD_CDAC_REG(lch))); in ssi_debug_gdd_show()
112 readw(gdd + SSI_GDD_CLNK_CTRL_REG(lch))); in ssi_debug_gdd_show()
227 csr = readw(omap_ssi->gdd + SSI_GDD_CSR_REG(lch)); in ssi_gdd_complete()
/drivers/atm/
Diphase.c1031 tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
1033 tcq_wr_ptr, readw(iadev->seg_ram+tcq_wr_ptr),
1034 readw(iadev->seg_ram+tcq_wr_ptr-2));
1037 tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);
1038 tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);
1043 printk("TCQ slot %d desc = %d Addr = %p\n", i++, readw(tmp), tmp);
1065 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1070 vci = readw(iadev->reass_ram+excpq_rd_ptr);
1071 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1074 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
[all …]
/drivers/mmc/host/
Dsdhci-pxav2.c69 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav2_reset()
81 tmp = readw(host->ioaddr + SD_FIFO_PARAM); in pxav2_reset()
85 tmp = readw(host->ioaddr + SD_FIFO_PARAM); in pxav2_reset()
99 tmp = readw(host->ioaddr + SD_CE_ATA_2); in pxav2_mmc_set_bus_width()

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