Searched refs:parents (Results 1 – 25 of 38) sorted by relevance
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/arch/arm/boot/dts/ |
D | stih407.dtsi | 28 assigned-clock-parents = <0>, 88 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
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D | exynos4412-odroid-common.dtsi | 48 assigned-clock-parents = <&clock CLK_FOUT_EPLL>, 152 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 160 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 168 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 176 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
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D | exynos4210-trats.dts | 162 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 170 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 178 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 186 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
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D | exynos4210-universal_c210.dts | 188 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 196 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 204 assigned-clock-parents = <&clock CLK_SCLK_MPLL>; 212 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
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D | stih410.dtsi | 119 assigned-clock-parents = <0>, 179 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
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D | exynos4412-trats2.dts | 236 assigned-clock-parents = <&clock CLK_XUSBXTI>, 301 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 321 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 402 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 410 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 418 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 426 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; 871 assigned-clock-parents = <&clock CLK_XUSBXTI>;
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D | imx7d-sdb.dts | 109 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 135 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 269 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
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D | stih418.dtsi | 105 assigned-clock-parents = <&clk_s_c0_pll1 0>;
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D | imx6qdl-sabreauto.dtsi | 119 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, 147 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
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D | rk3288-veyron.dtsi | 384 /* We need to go faster than 24MHz, so adjust clock parents / rates */ 419 assigned-clock-parents = <&cru SCLK_OTGPHY0>;
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D | exynos3250.dtsi | 200 assigned-clock-parents = <&cmu CLK_FIN_PLL>, 274 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
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D | rk3288-rock2-som.dtsi | 93 assigned-clock-parents = <&ext_gmac>;
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D | rk3288-evb-rk808.dts | 256 assigned-clock-parents = <&ext_gmac>;
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D | dra72-evm.dts | 802 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; 820 assigned-clock-parents = <&atl_clkin2_ck>;
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D | exynos5422-odroidxu3-common.dtsi | 63 assigned-clock-parents = <&clock CLK_FIN_PLL>,
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D | dra7-evm.dts | 877 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; 895 assigned-clock-parents = <&atl_clkin2_ck>;
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D | vexpress-v2m-rs1.dtsi | 105 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
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D | rk3288-r89.dts | 135 assigned-clock-parents = <&ext_gmac>;
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D | vexpress-v2m.dtsi | 104 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
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D | imx6qdl-sabresd.dtsi | 147 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
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/arch/x86/kvm/ |
D | mmu.c | 1973 #define for_each_sp(pvec, sp, parents, i) \ argument 1974 for (i = mmu_pages_next(&pvec, &parents, -1), \ 1977 i = mmu_pages_next(&pvec, &parents, i)) 1980 struct mmu_page_path *parents, in mmu_pages_next() argument 1989 parents->idx[0] = pvec->page[n].idx; in mmu_pages_next() 1993 parents->parent[sp->role.level-2] = sp; in mmu_pages_next() 1994 parents->idx[sp->role.level-1] = pvec->page[n].idx; in mmu_pages_next() 2000 static void mmu_pages_clear_parents(struct mmu_page_path *parents) in mmu_pages_clear_parents() argument 2006 unsigned int idx = parents->idx[level]; in mmu_pages_clear_parents() 2008 sp = parents->parent[level]; in mmu_pages_clear_parents() [all …]
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/arch/arm64/boot/dts/arm/ |
D | rtsm_ve-motherboard.dtsi | 78 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
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D | juno-motherboard.dtsi | 155 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
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D | vexpress-v2m-rs1.dtsi | 105 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
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/arch/arm64/boot/dts/rockchip/ |
D | rk3368-r88.dts | 243 assigned-clock-parents = <&cru PLL_CPLL>;
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