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Searched refs:INTEL_INFO (Results 1 – 25 of 41) sorted by relevance

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/drivers/gpu/drm/i915/
Di915_drv.h148 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
270 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
273 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
277 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
2454 #define INTEL_INFO(p) (&__I915__(p)->info) macro
2455 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2460 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2462 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2465 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2466 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
[all …]
Di915_suspend.c37 if (INTEL_INFO(dev)->gen <= 4) in i915_save_display()
43 else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) in i915_save_display()
60 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) in i915_save_display()
70 if (INTEL_INFO(dev)->gen <= 4) in i915_restore_display()
78 else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) in i915_restore_display()
98 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) in i915_restore_display()
118 if (INTEL_INFO(dev)->gen < 7) in i915_save_state()
164 if (INTEL_INFO(dev)->gen < 7) in i915_restore_state()
Di915_gem_tiling.c80 if (INTEL_INFO(dev)->gen >= 7) { in i915_tiling_ok()
83 } else if (INTEL_INFO(dev)->gen >= 4) { in i915_tiling_ok()
103 if (INTEL_INFO(dev)->gen >= 4) { in i915_tiling_ok()
125 if (INTEL_INFO(obj->base.dev)->gen >= 4) in i915_gem_object_fence_ok()
128 if (INTEL_INFO(obj->base.dev)->gen == 3) { in i915_gem_object_fence_ok()
Di915_dma.c109 value = INTEL_INFO(dev)->gen >= 4; in i915_getparam()
157 value = INTEL_INFO(dev)->subslice_total; in i915_getparam()
162 value = INTEL_INFO(dev)->eu_total; in i915_getparam()
210 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_alloc_mchbar_resource()
215 if (INTEL_INFO(dev)->gen >= 4) in intel_alloc_mchbar_resource()
242 if (INTEL_INFO(dev)->gen >= 4) in intel_alloc_mchbar_resource()
256 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_setup_mchbar()
296 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_teardown_mchbar()
422 if (INTEL_INFO(dev)->num_pipes == 0) in i915_load_modeset_init()
794 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) && in intel_device_info_runtime_init()
[all …]
Dintel_fbc.c531 if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) in intel_fbc_find_crtc()
557 if (INTEL_INFO(dev_priv)->gen > 4) in multiple_pipes_ok()
610 if (ret && INTEL_INFO(dev_priv)->gen <= 4) { in find_compression_threshold()
637 if (INTEL_INFO(dev_priv)->gen >= 5) in intel_fbc_alloc_cfb()
734 if (INTEL_INFO(dev_priv)->gen >= 7) in intel_fbc_calculate_cfb_size()
813 if (INTEL_INFO(dev_priv)->gen >= 8 || IS_HASWELL(dev_priv)) { in intel_fbc_hw_tracking_covers_screen()
816 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { in intel_fbc_hw_tracking_covers_screen()
910 if ((INTEL_INFO(dev_priv)->gen < 4 || HAS_DDI(dev_priv)) && in __intel_fbc_update()
924 if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) && in __intel_fbc_update()
1099 if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) in intel_fbc_init()
[all …]
Dintel_ringbuffer.c460 if (INTEL_INFO(ring->dev)->gen >= 8) in intel_ring_get_active_head()
463 else if (INTEL_INFO(ring->dev)->gen >= 4) in intel_ring_get_active_head()
477 if (INTEL_INFO(ring->dev)->gen >= 4) in ring_setup_phys_status_page()
528 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { in intel_ring_setup_status_page()
666 if (INTEL_INFO(dev)->gen >= 5) { in intel_fini_pipe_control()
1168 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) in init_render_ring()
1177 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) in init_render_ring()
1182 if (INTEL_INFO(dev)->gen == 6) in init_render_ring()
1202 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) in init_render_ring()
1235 num_rings = hweight32(INTEL_INFO(dev)->ring_mask); in gen8_rcs_signal()
[all …]
Di915_gpu_error.c264 if (INTEL_INFO(dev)->gen >= 4) { in i915_ring_error_state()
272 if (INTEL_INFO(dev)->gen >= 6) { in i915_ring_error_state()
290 if (INTEL_INFO(dev)->gen >= 8) { in i915_ring_error_state()
371 if (INTEL_INFO(dev)->gen >= 8) { in i915_error_state_to_str()
390 if (INTEL_INFO(dev)->gen >= 6) { in i915_error_state_to_str()
393 if (INTEL_INFO(dev)->gen >= 8) in i915_error_state_to_str()
400 if (INTEL_INFO(dev)->gen == 7) in i915_error_state_to_str()
800 } else if (INTEL_INFO(dev)->gen >= 6) { in i915_gem_record_fences()
864 if (INTEL_INFO(dev)->gen >= 6) { in i915_record_ring_state()
867 if (INTEL_INFO(dev)->gen >= 8) in i915_record_ring_state()
[all …]
Di915_gem_context.c114 switch (INTEL_INFO(dev)->gen) { in get_context_size()
195 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) { in i915_gem_alloc_context_obj()
525 hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 : in mi_set_context()
541 if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8) in mi_set_context()
543 else if (INTEL_INFO(ring->dev)->gen < 8) in mi_set_context()
548 if (INTEL_INFO(ring->dev)->gen >= 7) in mi_set_context()
556 if (INTEL_INFO(ring->dev)->gen >= 7) { in mi_set_context()
582 if (INTEL_INFO(ring->dev)->gen >= 7) { in mi_set_context()
625 if (INTEL_INFO(ring->dev)->gen < 8) in needs_pd_load_pre()
Di915_irq.c288 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; in gen6_pm_iir()
293 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; in gen6_pm_imr()
298 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; in gen6_pm_ier()
387 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) in gen6_sanitize_rps_pm_mask()
390 if (INTEL_INFO(dev_priv)->gen >= 8) in gen6_sanitize_rps_pm_mask()
599 if (INTEL_INFO(dev)->gen >= 4) in i915_enable_asle_pipestat()
820 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in i915_get_crtc_scanoutpos()
882 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { in i915_get_crtc_scanoutpos()
917 if (pipe >= INTEL_INFO(dev)->num_pipes) { in i915_get_vblank_timestamp()
1551 if (INTEL_INFO(dev)->gen >= 3) in i9xx_pipe_crc_irq_handler()
[all …]
Di915_debugfs.c79 const struct intel_device_info *info = INTEL_INFO(dev); in i915_capabilities()
617 if (INTEL_INFO(dev)->gen >= 4) in i915_gem_pageflip_info()
814 } else if (INTEL_INFO(dev)->gen >= 8) { in i915_interrupt_info()
935 if (INTEL_INFO(dev)->gen >= 6) { in i915_interrupt_info()
1604 else if (INTEL_INFO(dev)->gen >= 6) in i915_drpc_info()
1645 if (INTEL_INFO(dev_priv)->gen >= 7) in i915_fbc_status()
1661 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) in i915_fbc_fc_get()
1675 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) in i915_fbc_fc_set()
1711 if (INTEL_INFO(dev)->gen >= 8) { in i915_ips_status()
2179 } else if (INTEL_INFO(dev)->gen >= 6) { in i915_swizzle_info()
[all …]
Dintel_display.c1138 if (INTEL_INFO(dev)->gen >= 4) { in intel_wait_for_pipe_off()
1261 if (INTEL_INFO(dev_priv->dev)->gen == 5) in assert_fdi_tx_pll_enabled()
1393 if (INTEL_INFO(dev)->gen >= 4) { in assert_planes_disabled()
1418 if (INTEL_INFO(dev)->gen >= 9) { in assert_sprites_disabled()
1432 } else if (INTEL_INFO(dev)->gen >= 7) { in assert_sprites_disabled()
1437 } else if (INTEL_INFO(dev)->gen >= 5) { in assert_sprites_disabled()
1698 BUG_ON(INTEL_INFO(dev)->gen >= 5); in i9xx_enable_pll()
1730 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_enable_pll()
1930 if (INTEL_INFO(dev)->gen < 5) in intel_disable_shared_dpll()
2212 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) in need_vtd_wa()
[all …]
Dintel_lrc.c248 if (INTEL_INFO(dev)->gen >= 9) in intel_sanitize_enable_execlists()
1417 if (INTEL_INFO(ring->dev)->gen > 9) { in intel_init_workaround_bb()
1419 INTEL_INFO(ring->dev)->gen); in intel_init_workaround_bb()
1439 if (INTEL_INFO(ring->dev)->gen == 8) { in intel_init_workaround_bb()
1453 } else if (INTEL_INFO(ring->dev)->gen == 9) { in intel_init_workaround_bb()
1742 vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 && in gen8_emit_flush_render()
1984 if (INTEL_INFO(dev)->gen >= 9) in logical_render_ring_init()
2209 if (INTEL_INFO(dev)->gen < 9) in make_rpcs()
2218 if (INTEL_INFO(dev)->has_slice_pg) { in make_rpcs()
2220 rpcs |= INTEL_INFO(dev)->slice_total << in make_rpcs()
[all …]
Di915_gem_stolen.c59 if (INTEL_INFO(dev_priv)->gen == 8 && start < 4096) in i915_gem_stolen_insert_node_in_range()
106 if (INTEL_INFO(dev)->gen >= 3) { in i915_stolen_to_physical()
199 if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) { in i915_stolen_to_physical()
409 if (intel_iommu_gfx_mapped && INTEL_INFO(dev)->gen < 8) { in i915_gem_init_stolen()
424 switch (INTEL_INFO(dev_priv)->gen) { in i915_gem_init_stolen()
Dintel_pm.c1047 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; in vlv_invert_wms()
1079 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; in vlv_compute_wm()
1831 if (INTEL_INFO(dev)->gen >= 8) in ilk_display_fifo_size()
1833 else if (INTEL_INFO(dev)->gen >= 7) in ilk_display_fifo_size()
1842 if (INTEL_INFO(dev)->gen >= 8) in ilk_plane_wm_reg_max()
1845 else if (INTEL_INFO(dev)->gen >= 7) in ilk_plane_wm_reg_max()
1859 if (INTEL_INFO(dev)->gen >= 7) in ilk_cursor_wm_reg_max()
1867 if (INTEL_INFO(dev)->gen >= 8) in ilk_fbc_wm_reg_max()
1888 fifo_size /= INTEL_INFO(dev)->num_pipes; in ilk_plane_wm_max()
1895 if (INTEL_INFO(dev)->gen <= 6) in ilk_plane_wm_max()
[all …]
Di915_gem_fence.c65 if (INTEL_INFO(dev)->gen >= 6) { in i965_write_fence_reg()
212 else if (INTEL_INFO(dev)->gen >= 4) in i915_gem_write_fence()
556 if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) { in i915_gem_detect_bit_6_swizzle()
566 } else if (INTEL_INFO(dev)->gen >= 6) { in i915_gem_detect_bit_6_swizzle()
Dintel_lvds.c118 if (INTEL_INFO(dev)->gen < 4) { in intel_lvds_get_config()
186 if (INTEL_INFO(dev)->gen == 4) { in intel_pre_enable_lvds()
312 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { in intel_lvds_compute_config()
923 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) in intel_lvds_supported()
962 } else if (INTEL_INFO(dev_priv)->gen < 5) { in intel_lvds_init()
999 if (INTEL_INFO(dev_priv)->gen < 5 && in intel_lvds_init()
Di915_gem_gtt.c108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; in sanitize_enable_ppgtt()
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; in sanitize_enable_ppgtt()
118 if (INTEL_INFO(dev)->gen < 9 && in sanitize_enable_ppgtt()
123 if (enable_ppgtt == 1 && INTEL_INFO(dev)->gen != 9) in sanitize_enable_ppgtt()
131 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { in sanitize_enable_ppgtt()
144 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) in sanitize_enable_ppgtt()
427 const size_t count = INTEL_INFO(dev)->gen >= 8 ? in alloc_pt()
1217 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; in mark_tlbs_dirty()
2133 if (INTEL_INFO(dev)->gen < 8) in __hw_ppgtt_init()
2178 else if (INTEL_INFO(dev)->gen >= 8) in i915_ppgtt_init_hw()
[all …]
Di915_gem_execbuffer.c271 if (INTEL_INFO(dev)->gen >= 8) { in relocate_entry_cpu()
315 if (INTEL_INFO(dev)->gen >= 8) { in relocate_entry_gtt()
362 if (INTEL_INFO(dev)->gen >= 8) { in relocate_entry_clflush()
445 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { in i915_gem_execbuffer_relocate_entry()
698 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; in i915_gem_execbuffer_reserve()
1267 if (INTEL_INFO(dev)->gen < 4) { in i915_gem_ringbuffer_submission()
1272 if (INTEL_INFO(dev)->gen > 5 && in i915_gem_ringbuffer_submission()
1279 if (INTEL_INFO(dev)->gen >= 6) in i915_gem_ringbuffer_submission()
1712 if (INTEL_INFO(dev)->gen < 4) in i915_gem_execbuffer()
Dintel_psr.c184 aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ? in hsw_psr_enable_sink()
186 aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ? in hsw_psr_enable_sink()
194 if (INTEL_INFO(dev)->gen >= 9) { in hsw_psr_enable_sink()
413 if (INTEL_INFO(dev)->gen >= 9) in intel_psr_enable()
Dintel_uncore.c337 INTEL_INFO(dev)->gen >= 9) && in intel_uncore_ellc_detect()
1108 if (INTEL_INFO(dev_priv->dev)->gen <= 5) in intel_uncore_fw_domains_init()
1208 switch (INTEL_INFO(dev)->gen) { in intel_uncore_init()
1290 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) in i915_reg_read_ioctl()
1521 if (INTEL_INFO(dev)->gen >= 8) in intel_get_gpu_reset()
1523 else if (INTEL_INFO(dev)->gen >= 6) in intel_get_gpu_reset()
1531 else if (INTEL_INFO(dev)->gen >= 3) in intel_get_gpu_reset()
Di915_drv.c482 if (INTEL_INFO(dev)->num_pipes == 0) { in intel_detect_pch()
553 if (INTEL_INFO(dev)->gen < 6) in i915_semaphore_is_enabled()
569 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) in i915_semaphore_is_enabled()
716 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6)) in i915_drm_suspend_late()
960 if (INTEL_INFO(dev)->gen > 5) in i915_reset()
Dintel_fbdev.c494 num_connectors_enabled < INTEL_INFO(dev)->num_pipes) { in intel_fb_initial_config()
676 if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0)) in intel_fbdev_init()
689 INTEL_INFO(dev)->num_pipes, 4); in intel_fbdev_init()
Dintel_crt.c152 if (INTEL_INFO(dev)->gen >= 5) in intel_crt_set_dpms()
655 else if (INTEL_INFO(dev)->gen < 4) in intel_crt_detect()
718 if (INTEL_INFO(dev)->gen >= 5) { in intel_crt_reset()
Dintel_sprite.c792 if (INTEL_INFO(dev)->gen >= 9) { in intel_check_sprite_plane()
909 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || in intel_check_sprite_plane()
1066 if (INTEL_INFO(dev)->gen < 5) in intel_plane_init()
1080 switch (INTEL_INFO(dev)->gen) { in intel_plane_init()
Di915_gem_render_state.c52 so->gen = INTEL_INFO(dev)->gen; in render_state_init()

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