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Searched refs:radeon_crtc (Results 1 – 25 of 32) sorted by relevance

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/drivers/gpu/drm/radeon/
Dradeon_cursor.c33 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_lock_cursor() local
37 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset); in radeon_lock_cursor()
42 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
44 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); in radeon_lock_cursor()
49 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
51 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); in radeon_lock_cursor()
56 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); in radeon_lock_cursor()
62 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_hide_cursor() local
66 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset, in radeon_hide_cursor()
70 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, in radeon_hide_cursor()
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Datombios_crtc.c40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_overscan_setup() local
47 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
49 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); in atombios_overscan_setup()
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); in atombios_overscan_setup()
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in atombios_scaler_setup() local
87 to_radeon_encoder(radeon_crtc->encoder); in atombios_scaler_setup()
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) in atombios_scaler_setup()
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Dradeon_display.c42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in avivo_crtc_load_lut() local
47 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in avivo_crtc_load_lut()
48 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
58 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); in avivo_crtc_load_lut()
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Dradeon_legacy_crtc.c38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_overscan_setup() local
40 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
41 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
42 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_legacy_rmx_mode_set() local
62 struct drm_display_mode *native_mode = &radeon_crtc->native_mode; in radeon_legacy_rmx_mode_set()
125 switch (radeon_crtc->rmx_type) { in radeon_legacy_rmx_mode_set()
295 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_crtc_dpms() local
301 if (radeon_crtc->crtc_id) in radeon_crtc_dpms()
323 radeon_crtc->enabled = true; in radeon_crtc_dpms()
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Drs600.c115 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip() local
116 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rs600_page_flip()
121 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
124 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
126 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rs600_page_flip()
131 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rs600_page_flip()
139 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rs600_page_flip()
144 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip_pending() local
147 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rs600_page_flip_pending()
313 struct radeon_crtc *radeon_crtc; in rs600_pm_prepare() local
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Dradeon_legacy_encoders.c182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_lvds_mode_set() local
220 if (radeon_crtc->crtc_id == 0) { in radeon_legacy_lvds_mode_set()
241 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_lvds_mode_set()
243 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_lvds_mode_set()
583 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_primary_dac_mode_set() local
589 if (radeon_crtc->crtc_id == 0) { in radeon_legacy_primary_dac_mode_set()
629 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_primary_dac_mode_set()
631 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); in radeon_legacy_primary_dac_mode_set()
780 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_tmds_int_mode_set() local
847 if (radeon_crtc->crtc_id == 0) { in radeon_legacy_tmds_int_mode_set()
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Dradeon_legacy_tv.c239 struct radeon_crtc *radeon_crtc; in radeon_legacy_tv_get_std_mode() local
244 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); in radeon_legacy_tv_get_std_mode()
245 if (radeon_crtc->crtc_id == 1) in radeon_legacy_tv_get_std_mode()
427 struct radeon_crtc *radeon_crtc; in radeon_legacy_tv_init_restarts() local
436 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); in radeon_legacy_tv_init_restarts()
437 if (radeon_crtc->crtc_id == 1) in radeon_legacy_tv_init_restarts()
540 struct radeon_crtc *radeon_crtc; in radeon_legacy_tv_mode_set() local
557 radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_legacy_tv_mode_set()
603 if (radeon_crtc->crtc_id == 1) in radeon_legacy_tv_mode_set()
606 if (radeon_crtc->rmx_type != RMX_OFF) in radeon_legacy_tv_mode_set()
Dradeon_dp_mst.c360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_dp_mst_prepare_pll() local
363 struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder); in radeon_dp_mst_prepare_pll()
372 radeon_crtc->bpc = radeon_connector->base.display_info.bpc; in radeon_dp_mst_prepare_pll()
374 radeon_crtc->bpc = 8; in radeon_dp_mst_prepare_pll()
379 radeon_crtc->ss_enabled = in radeon_dp_mst_prepare_pll()
380 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, in radeon_dp_mst_prepare_pll()
395 struct radeon_crtc *radeon_crtc; in radeon_mst_encoder_dpms() local
422 radeon_crtc = to_radeon_crtc(crtc); in radeon_mst_encoder_dpms()
439 mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id); in radeon_mst_encoder_dpms()
447 dig_enc->linkb, radeon_crtc->crtc_id); in radeon_mst_encoder_dpms()
Datombios_encoders.c459 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_atom_get_bpc() local
460 bpc = radeon_crtc->bpc; in radeon_atom_get_bpc()
1053 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in atombios_dig_transmitter_setup2() local
1054 pll_id = radeon_crtc->pll_id; in atombios_dig_transmitter_setup2()
1541 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in atombios_yuv_setup() local
1557 (radeon_crtc->crtc_id << 18))); in atombios_yuv_setup()
1559 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); in atombios_yuv_setup()
1565 args.ucCRTC = radeon_crtc->crtc_id; in atombios_yuv_setup()
1864 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in atombios_set_encoder_crtc_source() local
1881 args.v1.ucCRTC = radeon_crtc->crtc_id; in atombios_set_encoder_crtc_source()
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Dradeon_audio.c67 struct radeon_crtc *crtc, unsigned int clock);
69 struct radeon_crtc *crtc, unsigned int clock);
71 struct radeon_crtc *crtc, unsigned int clock);
73 struct radeon_crtc *crtc, unsigned int clock);
75 struct radeon_crtc *crtc, unsigned int clock);
77 struct radeon_crtc *crtc, unsigned int clock);
499 struct radeon_crtc *crtc = to_radeon_crtc(encoder->crtc); in radeon_audio_set_dto()
661 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in radeon_hdmi_set_color_depth() local
662 bpc = radeon_crtc->bpc; in radeon_hdmi_set_color_depth()
Dradeon_mode.h45 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
247 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
327 struct radeon_crtc { struct
947 struct radeon_crtc *radeon_crtc);
949 struct radeon_crtc *radeon_crtc);
964 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
Dr600_dpm.c158 struct radeon_crtc *radeon_crtc; in r600_dpm_get_vblank_time() local
164 radeon_crtc = to_radeon_crtc(crtc); in r600_dpm_get_vblank_time()
165 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { in r600_dpm_get_vblank_time()
167 radeon_crtc->hw_mode.crtc_htotal * in r600_dpm_get_vblank_time()
168 (radeon_crtc->hw_mode.crtc_vblank_end - in r600_dpm_get_vblank_time()
169 radeon_crtc->hw_mode.crtc_vdisplay + in r600_dpm_get_vblank_time()
170 (radeon_crtc->v_border * 2)); in r600_dpm_get_vblank_time()
172 vblank_time_us = vblank_in_pixels * 1000 / radeon_crtc->hw_mode.clock; in r600_dpm_get_vblank_time()
185 struct radeon_crtc *radeon_crtc; in r600_dpm_get_vrefresh() local
190 radeon_crtc = to_radeon_crtc(crtc); in r600_dpm_get_vrefresh()
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Devergreen.c1292 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in dce4_program_fmt() local
1340 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
1412 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip() local
1415 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in evergreen_page_flip()
1417 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in evergreen_page_flip()
1420 RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset); in evergreen_page_flip()
1433 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip_pending() local
1436 return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & in evergreen_page_flip_pending()
1664 struct radeon_crtc *radeon_crtc; in evergreen_pm_prepare() local
1669 radeon_crtc = to_radeon_crtc(crtc); in evergreen_pm_prepare()
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Devergreen_hdmi.c75 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in evergreen_hdmi_update_acr() local
76 bpc = radeon_crtc->bpc; in evergreen_hdmi_update_acr()
228 struct radeon_crtc *crtc, unsigned int clock) in dce4_hdmi_audio_set_dto()
271 struct radeon_crtc *crtc, unsigned int clock) in dce4_dp_audio_set_dto()
Drv770.c806 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rv770_page_flip() local
807 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); in rv770_page_flip()
812 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
815 if (radeon_crtc->crtc_id) { in rv770_page_flip()
822 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
824 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in rv770_page_flip()
829 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) in rv770_page_flip()
837 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in rv770_page_flip()
842 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rv770_page_flip_pending() local
845 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & in rv770_page_flip_pending()
Dradeon_device.c1611 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_suspend_kms() local
1615 if (radeon_crtc->cursor_bo) { in radeon_suspend_kms()
1616 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); in radeon_suspend_kms()
1728 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_resume_kms() local
1730 if (radeon_crtc->cursor_bo) { in radeon_resume_kms()
1731 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); in radeon_resume_kms()
1739 &radeon_crtc->cursor_addr); in radeon_resume_kms()
Dr100.c158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip() local
164 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
168 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) in r100_page_flip()
176 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); in r100_page_flip()
191 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in r100_page_flip_pending() local
194 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & in r100_page_flip_pending()
447 struct radeon_crtc *radeon_crtc; in r100_pm_prepare() local
452 radeon_crtc = to_radeon_crtc(crtc); in r100_pm_prepare()
453 if (radeon_crtc->enabled) { in r100_pm_prepare()
454 if (radeon_crtc->crtc_id) { in r100_pm_prepare()
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Dsi.c1912 struct radeon_crtc *radeon_crtc, in dce6_line_buffer_adjust() argument
1917 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce6_line_buffer_adjust()
1931 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust()
1944 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, in dce6_line_buffer_adjust()
1956 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust()
2252 struct radeon_crtc *radeon_crtc, in dce6_program_watermarks() argument
2255 struct drm_display_mode *mode = &radeon_crtc->base.mode; in dce6_program_watermarks()
2267 if (radeon_crtc->base.enabled && num_heads && mode) { in dce6_program_watermarks()
2296 wm_high.vsc = radeon_crtc->vsc; in dce6_program_watermarks()
2298 if (radeon_crtc->rmx_type != RMX_OFF) in dce6_program_watermarks()
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Ddce6_afmt.c269 struct radeon_crtc *crtc, unsigned int clock) in dce6_hdmi_audio_set_dto()
288 struct radeon_crtc *crtc, unsigned int clock) in dce6_dp_audio_set_dto()
Dradeon_pm.c1635 struct radeon_crtc *radeon_crtc; in radeon_pm_compute_clocks_old() local
1647 radeon_crtc = to_radeon_crtc(crtc); in radeon_pm_compute_clocks_old()
1648 if (radeon_crtc->enabled) { in radeon_pm_compute_clocks_old()
1649 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); in radeon_pm_compute_clocks_old()
1708 struct radeon_crtc *radeon_crtc; in radeon_pm_compute_clocks_dpm() local
1721 radeon_crtc = to_radeon_crtc(crtc); in radeon_pm_compute_clocks_dpm()
1723 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); in radeon_pm_compute_clocks_dpm()
Dradeon_audio.h55 struct radeon_crtc *crtc, unsigned int clock);
Dcik.c8994 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in dce8_program_fmt() local
9050 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt()
9067 struct radeon_crtc *radeon_crtc, in dce8_line_buffer_adjust() argument
9071 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce8_line_buffer_adjust()
9080 if (radeon_crtc->base.enabled && mode) { in dce8_line_buffer_adjust()
9100 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset, in dce8_line_buffer_adjust()
9112 if (radeon_crtc->base.enabled && mode) { in dce8_line_buffer_adjust()
9509 struct radeon_crtc *radeon_crtc, in dce8_program_watermarks() argument
9512 struct drm_display_mode *mode = &radeon_crtc->base.mode; in dce8_program_watermarks()
9519 if (radeon_crtc->base.enabled && num_heads && mode) { in dce8_program_watermarks()
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Drs780_dpm.c53 struct radeon_crtc *radeon_crtc; in rs780_get_pm_mode_parameters() local
63 radeon_crtc = to_radeon_crtc(crtc); in rs780_get_pm_mode_parameters()
64 pi->crtc_id = radeon_crtc->crtc_id; in rs780_get_pm_mode_parameters()
Dradeon_kms.c254 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_info_ioctl() local
255 *value = radeon_crtc->crtc_id; in radeon_info_ioctl()
Ddce3_1_afmt.c117 struct radeon_crtc *crtc, unsigned int clock) in dce3_2_audio_set_dto()

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