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Searched refs:rps (Results 1 – 25 of 37) sorted by relevance

12

/drivers/gpu/drm/i915/
Di915_sysfs.c281 flush_delayed_work(&dev_priv->rps.delayed_resume_work); in gt_act_freq_mhz_show()
285 mutex_lock(&dev_priv->rps.hw_lock); in gt_act_freq_mhz_show()
300 mutex_unlock(&dev_priv->rps.hw_lock); in gt_act_freq_mhz_show()
315 flush_delayed_work(&dev_priv->rps.delayed_resume_work); in gt_cur_freq_mhz_show()
319 mutex_lock(&dev_priv->rps.hw_lock); in gt_cur_freq_mhz_show()
320 ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq); in gt_cur_freq_mhz_show()
321 mutex_unlock(&dev_priv->rps.hw_lock); in gt_cur_freq_mhz_show()
337 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); in vlv_rpe_freq_mhz_show()
347 flush_delayed_work(&dev_priv->rps.delayed_resume_work); in gt_max_freq_mhz_show()
349 mutex_lock(&dev_priv->rps.hw_lock); in gt_max_freq_mhz_show()
[all …]
Dintel_pm.c252 mutex_lock(&dev_priv->rps.hw_lock); in chv_set_memory_dvfs()
267 mutex_unlock(&dev_priv->rps.hw_lock); in chv_set_memory_dvfs()
274 mutex_lock(&dev_priv->rps.hw_lock); in chv_set_memory_pm5()
283 mutex_unlock(&dev_priv->rps.hw_lock); in chv_set_memory_pm5()
2068 mutex_lock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
2072 mutex_unlock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
2089 mutex_lock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
2093 mutex_unlock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
4039 mutex_lock(&dev_priv->rps.hw_lock); in vlv_wm_get_hw_state()
4069 mutex_unlock(&dev_priv->rps.hw_lock); in vlv_wm_get_hw_state()
[all …]
Di915_debugfs.c1133 flush_delayed_work(&dev_priv->rps.delayed_resume_work); in i915_frequency_info()
1242 dev_priv->rps.up_threshold); in i915_frequency_info()
1251 dev_priv->rps.down_threshold); in i915_frequency_info()
1270 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); in i915_frequency_info()
1273 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq)); in i915_frequency_info()
1276 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq)); in i915_frequency_info()
1278 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq)); in i915_frequency_info()
1280 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); in i915_frequency_info()
1283 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); in i915_frequency_info()
1287 mutex_lock(&dev_priv->rps.hw_lock); in i915_frequency_info()
[all …]
Di915_irq.c359 dev_priv->rps.pm_iir = 0; in gen6_reset_rps_interrupts()
369 WARN_ON(dev_priv->rps.pm_iir); in gen6_enable_rps_interrupts()
371 dev_priv->rps.interrupts_enabled = true; in gen6_enable_rps_interrupts()
401 dev_priv->rps.interrupts_enabled = false; in gen6_disable_rps_interrupts()
404 cancel_work_sync(&dev_priv->rps.work); in gen6_disable_rps_interrupts()
999 memset(&dev_priv->rps.ei, 0, sizeof(dev_priv->rps.ei)); in gen6_rps_reset_ei()
1004 const struct intel_rps_ei *prev = &dev_priv->rps.ei; in vlv_wa_c0_ei()
1035 if (c0 > time * dev_priv->rps.up_threshold) in vlv_wa_c0_ei()
1037 else if (c0 < time * dev_priv->rps.down_threshold) in vlv_wa_c0_ei()
1041 dev_priv->rps.ei = now; in vlv_wa_c0_ei()
[all …]
Dintel_sideband.c82 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in vlv_punit_read()
94 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in vlv_punit_write()
122 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in vlv_nc_read()
Dintel_runtime_pm.c786 mutex_lock(&dev_priv->rps.hw_lock); in vlv_set_power_well()
807 mutex_unlock(&dev_priv->rps.hw_lock); in vlv_set_power_well()
840 mutex_lock(&dev_priv->rps.hw_lock); in vlv_power_well_enabled()
859 mutex_unlock(&dev_priv->rps.hw_lock); in vlv_power_well_enabled()
1316 mutex_lock(&dev_priv->rps.hw_lock); in chv_pipe_power_well_enabled()
1333 mutex_unlock(&dev_priv->rps.hw_lock); in chv_pipe_power_well_enabled()
1348 mutex_lock(&dev_priv->rps.hw_lock); in chv_set_pipe_power_well()
1369 mutex_unlock(&dev_priv->rps.hw_lock); in chv_set_pipe_power_well()
Di915_gem.c1244 struct intel_rps_client *rps) in __i915_wait_request() argument
1277 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); in __i915_wait_request()
1548 struct intel_rps_client *rps, in i915_gem_object_wait_rendering__nonblocking() argument
1592 NULL, rps); in i915_gem_object_wait_rendering__nonblocking()
1607 return &fpriv->rps; in to_rps_client()
3229 &i915->rps.semaphores); in __i915_gem_object_sync()
5164 if (!list_empty(&file_priv->rps.link)) { in i915_gem_release()
5165 spin_lock(&to_i915(dev)->rps.client_lock); in i915_gem_release()
5166 list_del(&file_priv->rps.link); in i915_gem_release()
5167 spin_unlock(&to_i915(dev)->rps.client_lock); in i915_gem_release()
[all …]
/drivers/gpu/drm/radeon/
Drs780_dpm.c34 static struct igp_ps *rs780_get_ps(struct radeon_ps *rps) in rs780_get_ps() argument
36 struct igp_ps *ps = rps->ps_priv; in rs780_get_ps()
718 struct radeon_ps *rps, in rs780_parse_pplib_non_clock_info() argument
722 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); in rs780_parse_pplib_non_clock_info()
723 rps->class = le16_to_cpu(non_clock_info->usClassification); in rs780_parse_pplib_non_clock_info()
724 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in rs780_parse_pplib_non_clock_info()
727 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rs780_parse_pplib_non_clock_info()
728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rs780_parse_pplib_non_clock_info()
730 rps->vclk = 0; in rs780_parse_pplib_non_clock_info()
731 rps->dclk = 0; in rs780_parse_pplib_non_clock_info()
[all …]
Dtrinity_dpm.c347 static struct trinity_ps *trinity_get_ps(struct radeon_ps *rps) in trinity_get_ps() argument
349 struct trinity_ps *ps = rps->ps_priv; in trinity_get_ps()
869 struct radeon_ps *rps) in trinity_setup_uvd_clock_table() argument
871 struct trinity_ps *ps = trinity_get_ps(rps); in trinity_setup_uvd_clock_table()
895 static bool trinity_uvd_clocks_zero(struct radeon_ps *rps) in trinity_uvd_clocks_zero() argument
897 if ((rps->vclk == 0) && (rps->dclk == 0)) in trinity_uvd_clocks_zero()
1067 struct radeon_ps *rps) in trinity_update_current_ps() argument
1069 struct trinity_ps *new_ps = trinity_get_ps(rps); in trinity_update_current_ps()
1072 pi->current_rps = *rps; in trinity_update_current_ps()
1078 struct radeon_ps *rps) in trinity_update_requested_ps() argument
[all …]
Dsumo_dpm.c75 static struct sumo_ps *sumo_get_ps(struct radeon_ps *rps) in sumo_get_ps() argument
77 struct sumo_ps *ps = rps->ps_priv; in sumo_get_ps()
343 struct radeon_ps *rps) in sumo_program_bsp() argument
346 struct sumo_ps *ps = sumo_get_ps(rps); in sumo_program_bsp()
386 struct radeon_ps *rps) in sumo_program_at() argument
389 struct sumo_ps *ps = sumo_get_ps(rps); in sumo_program_at()
665 struct radeon_ps *rps) in sumo_patch_boost_state() argument
668 struct sumo_ps *new_ps = sumo_get_ps(rps); in sumo_patch_boost_state()
715 struct radeon_ps *rps, in sumo_enable_boost() argument
718 struct sumo_ps *new_ps = sumo_get_ps(rps); in sumo_enable_boost()
[all …]
Drv770_dpm.c48 struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps) in rv770_get_ps() argument
50 struct rv7xx_ps *ps = rps->ps_priv; in rv770_get_ps()
2145 struct radeon_ps *rps, in rv7xx_parse_pplib_non_clock_info() argument
2149 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); in rv7xx_parse_pplib_non_clock_info()
2150 rps->class = le16_to_cpu(non_clock_info->usClassification); in rv7xx_parse_pplib_non_clock_info()
2151 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in rv7xx_parse_pplib_non_clock_info()
2154 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in rv7xx_parse_pplib_non_clock_info()
2155 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in rv7xx_parse_pplib_non_clock_info()
2157 rps->vclk = 0; in rv7xx_parse_pplib_non_clock_info()
2158 rps->dclk = 0; in rv7xx_parse_pplib_non_clock_info()
[all …]
Drv6xx_dpm.c37 static struct rv6xx_ps *rv6xx_get_ps(struct radeon_ps *rps) in rv6xx_get_ps() argument
39 struct rv6xx_ps *ps = rps->ps_priv; in rv6xx_get_ps()
1796 struct radeon_ps *rps, in rv6xx_parse_pplib_non_clock_info() argument
1799 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); in rv6xx_parse_pplib_non_clock_info()
1800 rps->class = le16_to_cpu(non_clock_info->usClassification); in rv6xx_parse_pplib_non_clock_info()
1801 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in rv6xx_parse_pplib_non_clock_info()
1803 if (r600_is_uvd_state(rps->class, rps->class2)) { in rv6xx_parse_pplib_non_clock_info()
1804 rps->vclk = RV6XX_DEFAULT_VCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1805 rps->dclk = RV6XX_DEFAULT_DCLK_FREQ; in rv6xx_parse_pplib_non_clock_info()
1807 rps->vclk = 0; in rv6xx_parse_pplib_non_clock_info()
[all …]
Dni_dpm.c733 struct ni_ps *ni_get_ps(struct radeon_ps *rps) in ni_get_ps() argument
735 struct ni_ps *ps = rps->ps_priv; in ni_get_ps()
786 struct radeon_ps *rps) in ni_apply_state_adjust_rules() argument
788 struct ni_ps *ps = ni_get_ps(rps); in ni_apply_state_adjust_rules()
3562 struct radeon_ps *rps) in ni_update_current_ps() argument
3564 struct ni_ps *new_ps = ni_get_ps(rps); in ni_update_current_ps()
3568 eg_pi->current_rps = *rps; in ni_update_current_ps()
3574 struct radeon_ps *rps) in ni_update_requested_ps() argument
3576 struct ni_ps *new_ps = ni_get_ps(rps); in ni_update_requested_ps()
3580 eg_pi->requested_rps = *rps; in ni_update_requested_ps()
[all …]
Dkv_dpm.c242 static struct kv_ps *kv_get_ps(struct radeon_ps *rps) in kv_get_ps() argument
244 struct kv_ps *ps = rps->ps_priv; in kv_get_ps()
1139 struct radeon_ps *rps) in kv_update_current_ps() argument
1141 struct kv_ps *new_ps = kv_get_ps(rps); in kv_update_current_ps()
1144 pi->current_rps = *rps; in kv_update_current_ps()
1150 struct radeon_ps *rps) in kv_update_requested_ps() argument
1152 struct kv_ps *new_ps = kv_get_ps(rps); in kv_update_requested_ps()
1155 pi->requested_rps = *rps; in kv_update_requested_ps()
2583 struct radeon_ps *rps, in kv_parse_pplib_non_clock_info() argument
2587 struct kv_ps *ps = kv_get_ps(rps); in kv_parse_pplib_non_clock_info()
[all …]
Dbtc_dpm.c50 struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
2096 struct radeon_ps *rps) in btc_apply_state_adjust_rules() argument
2098 struct rv7xx_ps *ps = rv770_get_ps(rps); in btc_apply_state_adjust_rules()
2259 struct radeon_ps *rps) in btc_update_current_ps() argument
2261 struct rv7xx_ps *new_ps = rv770_get_ps(rps); in btc_update_current_ps()
2264 eg_pi->current_rps = *rps; in btc_update_current_ps()
2270 struct radeon_ps *rps) in btc_update_requested_ps() argument
2272 struct rv7xx_ps *new_ps = rv770_get_ps(rps); in btc_update_requested_ps()
2275 eg_pi->requested_rps = *rps; in btc_update_requested_ps()
2737 struct radeon_ps *rps = &eg_pi->current_rps; in btc_dpm_debugfs_print_current_performance_level() local
[all …]
Dsi_dpm.c1740 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
2990 struct radeon_ps *rps) in si_apply_state_adjust_rules() argument
2992 struct ni_ps *ps = ni_get_ps(rps); in si_apply_state_adjust_rules()
3057 if (rps->vce_active) { in si_apply_state_adjust_rules()
3058 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in si_apply_state_adjust_rules()
3059 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
3060 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3063 rps->evclk = 0; in si_apply_state_adjust_rules()
3064 rps->ecclk = 0; in si_apply_state_adjust_rules()
3071 if (rps->vclk || rps->dclk) { in si_apply_state_adjust_rules()
[all …]
Dci_dpm.c200 static struct ci_ps *ci_get_ps(struct radeon_ps *rps) in ci_get_ps() argument
202 struct ci_ps *ps = rps->ps_priv; in ci_get_ps()
793 struct radeon_ps *rps) in ci_apply_state_adjust_rules() argument
795 struct ci_ps *ps = ci_get_ps(rps); in ci_apply_state_adjust_rules()
802 if (rps->vce_active) { in ci_apply_state_adjust_rules()
803 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in ci_apply_state_adjust_rules()
804 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in ci_apply_state_adjust_rules()
806 rps->evclk = 0; in ci_apply_state_adjust_rules()
807 rps->ecclk = 0; in ci_apply_state_adjust_rules()
816 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) in ci_apply_state_adjust_rules()
[all …]
Dni_dpm.h237 struct radeon_ps *rps);
239 struct radeon_ps *rps);
/drivers/staging/comedi/drivers/
Ds626.c1560 uint32_t *rps; in s626_reset_adc() local
1570 rps = (uint32_t *)devpriv->rps_buf.logical_base; in s626_reset_adc()
1579 *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC; in s626_reset_adc()
1580 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; in s626_reset_adc()
1592 *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); in s626_reset_adc()
1593 *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL; in s626_reset_adc()
1594 *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); in s626_reset_adc()
1596 *rps++ = S626_GSEL_BIPOLAR5V; /* arbitrary immediate data value. */ in s626_reset_adc()
1597 *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; in s626_reset_adc()
1600 *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; in s626_reset_adc()
[all …]
/drivers/gpu/drm/amd/amdgpu/
Dcz_dpm.c48 static struct cz_ps *cz_get_ps(struct amdgpu_ps *rps) in cz_get_ps() argument
50 struct cz_ps *ps = rps->ps_priv; in cz_get_ps()
237 struct amdgpu_ps *rps, int index, in cz_parse_pplib_clock_info() argument
241 struct cz_ps *ps = cz_get_ps(rps); in cz_parse_pplib_clock_info()
259 struct amdgpu_ps *rps, in cz_parse_pplib_non_clock_info() argument
263 struct cz_ps *ps = cz_get_ps(rps); in cz_parse_pplib_non_clock_info()
265 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); in cz_parse_pplib_non_clock_info()
266 rps->class = le16_to_cpu(non_clock_info->usClassification); in cz_parse_pplib_non_clock_info()
267 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); in cz_parse_pplib_non_clock_info()
270 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); in cz_parse_pplib_non_clock_info()
[all …]
Dkv_dpm.c375 static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps) in kv_get_ps() argument
377 struct kv_ps *ps = rps->ps_priv; in kv_get_ps()
1228 struct amdgpu_ps *rps) in kv_update_current_ps() argument
1230 struct kv_ps *new_ps = kv_get_ps(rps); in kv_update_current_ps()
1233 pi->current_rps = *rps; in kv_update_current_ps()
1239 struct amdgpu_ps *rps) in kv_update_requested_ps() argument
1241 struct kv_ps *new_ps = kv_get_ps(rps); in kv_update_requested_ps()
1244 pi->requested_rps = *rps; in kv_update_requested_ps()
2680 struct amdgpu_ps *rps, in kv_parse_pplib_non_clock_info() argument
2684 struct kv_ps *ps = kv_get_ps(rps); in kv_parse_pplib_non_clock_info()
[all …]
Dci_dpm.c318 static struct ci_ps *ci_get_ps(struct amdgpu_ps *rps) in ci_get_ps() argument
320 struct ci_ps *ps = rps->ps_priv; in ci_get_ps()
910 struct amdgpu_ps *rps) in ci_apply_state_adjust_rules() argument
912 struct ci_ps *ps = ci_get_ps(rps); in ci_apply_state_adjust_rules()
919 if (rps->vce_active) { in ci_apply_state_adjust_rules()
920 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; in ci_apply_state_adjust_rules()
921 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in ci_apply_state_adjust_rules()
923 rps->evclk = 0; in ci_apply_state_adjust_rules()
924 rps->ecclk = 0; in ci_apply_state_adjust_rules()
933 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) in ci_apply_state_adjust_rules()
[all …]
Damdgpu_dpm.h58 struct amdgpu_ps *rps);
Damdgpu_dpm.c104 struct amdgpu_ps *rps) in amdgpu_dpm_print_ps_status() argument
107 if (rps == adev->pm.dpm.current_ps) in amdgpu_dpm_print_ps_status()
109 if (rps == adev->pm.dpm.requested_ps) in amdgpu_dpm_print_ps_status()
111 if (rps == adev->pm.dpm.boot_ps) in amdgpu_dpm_print_ps_status()
/drivers/scsi/aic94xx/
Daic94xx_dev.c183 if (rps_resp->rps.affil_valid) in asd_init_target_ddb()
185 if (rps_resp->rps.affil_supp) in asd_init_target_ddb()

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