| /virt/kvm/arm/hyp/ |
| D | vgic-v3-sr.c | 59 static void __hyp_text __gic_v3_set_lr(u64 val, int lr) in __gic_v3_set_lr() argument
63 write_gicreg(val, ICH_LR0_EL2); in __gic_v3_set_lr()
66 write_gicreg(val, ICH_LR1_EL2); in __gic_v3_set_lr()
69 write_gicreg(val, ICH_LR2_EL2); in __gic_v3_set_lr()
72 write_gicreg(val, ICH_LR3_EL2); in __gic_v3_set_lr()
75 write_gicreg(val, ICH_LR4_EL2); in __gic_v3_set_lr()
78 write_gicreg(val, ICH_LR5_EL2); in __gic_v3_set_lr()
81 write_gicreg(val, ICH_LR6_EL2); in __gic_v3_set_lr()
84 write_gicreg(val, ICH_LR7_EL2); in __gic_v3_set_lr()
87 write_gicreg(val, ICH_LR8_EL2); in __gic_v3_set_lr()
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| D | timer-sr.c | 25 u64 val; in __timer_disable_traps() local
28 val = read_sysreg(cnthctl_el2); in __timer_disable_traps()
29 val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN; in __timer_disable_traps()
30 write_sysreg(val, cnthctl_el2); in __timer_disable_traps()
39 u64 val; in __timer_enable_traps() local
45 val = read_sysreg(cnthctl_el2); in __timer_enable_traps()
46 val &= ~CNTHCTL_EL1PCEN; in __timer_enable_traps()
47 val |= CNTHCTL_EL1PCTEN; in __timer_enable_traps()
48 write_sysreg(val, cnthctl_el2); in __timer_enable_traps()
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| /virt/kvm/arm/ |
| D | psci.c | 225 unsigned long val; in kvm_psci_0_2_call() local
234 val = KVM_ARM_PSCI_0_2; in kvm_psci_0_2_call()
238 val = kvm_psci_vcpu_suspend(vcpu); in kvm_psci_0_2_call()
242 val = PSCI_RET_SUCCESS; in kvm_psci_0_2_call()
247 val = kvm_psci_vcpu_on(vcpu); in kvm_psci_0_2_call()
252 val = kvm_psci_vcpu_affinity_info(vcpu); in kvm_psci_0_2_call()
260 val = PSCI_0_2_TOS_MP; in kvm_psci_0_2_call()
274 val = PSCI_RET_INTERNAL_FAILURE; in kvm_psci_0_2_call()
283 val = PSCI_RET_INTERNAL_FAILURE; in kvm_psci_0_2_call()
287 val = PSCI_RET_NOT_SUPPORTED; in kvm_psci_0_2_call()
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| D | pmu.c | 162 void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val) in kvm_pmu_set_counter_value() argument
168 __vcpu_sys_reg(vcpu, reg) += (s64)val - kvm_pmu_get_counter_value(vcpu, select_idx); in kvm_pmu_set_counter_value()
196 u64 counter, reg, val; in kvm_pmu_stop_counter() local
206 val = counter; in kvm_pmu_stop_counter()
209 val = lower_32_bits(counter); in kvm_pmu_stop_counter()
212 __vcpu_sys_reg(vcpu, reg) = val; in kvm_pmu_stop_counter()
266 u64 val = __vcpu_sys_reg(vcpu, PMCR_EL0) >> ARMV8_PMU_PMCR_N_SHIFT; in kvm_pmu_valid_counter_mask() local
268 val &= ARMV8_PMU_PMCR_N_MASK; in kvm_pmu_valid_counter_mask()
269 if (val == 0) in kvm_pmu_valid_counter_mask()
272 return GENMASK(val - 1, 0) | BIT(ARMV8_PMU_CYCLE_IDX); in kvm_pmu_valid_counter_mask()
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| D | arch_timer.c | 49 u64 val);
803 u64 val; in kvm_arm_timer_read() local
807 val = timer->cnt_cval - kvm_phys_timer_read() + timer->cntvoff; in kvm_arm_timer_read()
808 val &= lower_32_bits(val); in kvm_arm_timer_read()
812 val = read_timer_ctl(timer); in kvm_arm_timer_read()
816 val = timer->cnt_cval; in kvm_arm_timer_read()
820 val = kvm_phys_timer_read() - timer->cntvoff; in kvm_arm_timer_read()
827 return val; in kvm_arm_timer_read()
834 u64 val; in kvm_arm_timer_read_sysreg() local
839 val = kvm_arm_timer_read(vcpu, vcpu_get_timer(vcpu, tmr), treg); in kvm_arm_timer_read_sysreg()
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| /virt/kvm/arm/vgic/ |
| D | vgic-mmio-v2.c | 54 unsigned long val) in vgic_mmio_write_v2_misc() argument
61 dist->enabled = val & GICD_ENABLE; in vgic_mmio_write_v2_misc()
74 unsigned long val) in vgic_mmio_uaccess_write_v2_misc() argument
78 if (val != vgic_mmio_read_v2_misc(vcpu, addr, len)) in vgic_mmio_uaccess_write_v2_misc()
94 vgic_mmio_write_v2_misc(vcpu, addr, len, val); in vgic_mmio_uaccess_write_v2_misc()
100 unsigned long val) in vgic_mmio_uaccess_write_v2_group() argument
103 vgic_mmio_write_group(vcpu, addr, len, val); in vgic_mmio_uaccess_write_v2_group()
110 unsigned long val) in vgic_mmio_write_sgir() argument
113 int intid = val & 0xf; in vgic_mmio_write_sgir()
114 int targets = (val >> 16) & 0xff; in vgic_mmio_write_sgir()
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| D | vgic-mmio.h | 21 unsigned int len, unsigned long val);
24 unsigned long val);
30 unsigned int len, unsigned long val);
33 unsigned long val);
106 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len);
115 unsigned long val);
124 unsigned int len, unsigned long val);
127 unsigned int len, unsigned long val);
133 unsigned int len, unsigned long val);
140 unsigned long val);
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| D | vgic-mmio.c | 30 unsigned int len, unsigned long val) in vgic_mmio_write_wi() argument
36 unsigned int len, unsigned long val) in vgic_mmio_uaccess_write_wi() argument
63 unsigned int len, unsigned long val) in vgic_mmio_write_group() argument
73 irq->group = !!(val & BIT(i)); in vgic_mmio_write_group()
106 unsigned long val) in vgic_mmio_write_senable() argument
112 for_each_set_bit(i, &val, len * 8) { in vgic_mmio_write_senable()
141 unsigned long val) in vgic_mmio_write_cenable() argument
147 for_each_set_bit(i, &val, len * 8) { in vgic_mmio_write_cenable()
222 unsigned long val) in vgic_mmio_write_spending() argument
229 for_each_set_bit(i, &val, len * 8) { in vgic_mmio_write_spending()
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| D | vgic-v3.c | 43 u64 val = cpuif->vgic_lr[lr]; in vgic_v3_fold_lr_state() local
48 cpuid = val & GICH_LR_PHYSID_CPUID; in vgic_v3_fold_lr_state()
52 intid = val & ICH_LR_VIRTUAL_ID_MASK; in vgic_v3_fold_lr_state()
54 intid = val & GICH_LR_VIRTUALID; in vgic_v3_fold_lr_state()
59 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid)) in vgic_v3_fold_lr_state()
70 irq->active = !!(val & ICH_LR_ACTIVE_BIT); in vgic_v3_fold_lr_state()
77 (val & ICH_LR_PENDING_BIT)) { in vgic_v3_fold_lr_state()
87 if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE)) in vgic_v3_fold_lr_state()
103 if (vgic_irq_is_mapped_level(irq) && (val & ICH_LR_PENDING_BIT)) { in vgic_v3_fold_lr_state()
121 u64 val = irq->intid; in vgic_v3_populate_lr() local
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| D | vgic-v2.c | 14 static inline void vgic_v2_write_lr(int lr, u32 val) in vgic_v2_write_lr() argument
18 writel_relaxed(val, base + GICH_LR0 + (lr * 4)); in vgic_v2_write_lr()
60 u32 val = cpuif->vgic_lr[lr]; in vgic_v2_fold_lr_state() local
61 u32 cpuid, intid = val & GICH_LR_VIRTUALID; in vgic_v2_fold_lr_state()
65 cpuid = val & GICH_LR_PHYSID_CPUID; in vgic_v2_fold_lr_state()
70 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid)) in vgic_v2_fold_lr_state()
79 irq->active = !!(val & GICH_LR_ACTIVE_BIT); in vgic_v2_fold_lr_state()
86 (val & GICH_LR_PENDING_BIT)) { in vgic_v2_fold_lr_state()
96 if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE)) in vgic_v2_fold_lr_state()
112 if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT)) { in vgic_v2_fold_lr_state()
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| D | vgic-mmio-v3.c | 28 unsigned long val) in update_64bit_reg() argument
34 val &= GENMASK_ULL(len * 8 - 1, 0); in update_64bit_reg()
36 return reg | ((u64)val << lower); in update_64bit_reg()
97 unsigned long val) in vgic_mmio_write_v3_misc() argument
104 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1; in vgic_mmio_write_v3_misc()
117 unsigned long val) in vgic_mmio_uaccess_write_v3_misc() argument
121 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len)) in vgic_mmio_uaccess_write_v3_misc()
125 vgic_mmio_write_v3_misc(vcpu, addr, len, val); in vgic_mmio_uaccess_write_v3_misc()
149 unsigned long val) in vgic_mmio_write_irouter() argument
167 irq->mpidr = val & GENMASK(23, 0); in vgic_mmio_write_irouter()
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| D | vgic.h | 39 #define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \ argument
40 VGIC_AFFINITY_LEVEL(val, 1) | \
41 VGIC_AFFINITY_LEVEL(val, 2) | \
42 VGIC_AFFINITY_LEVEL(val, 3))
183 int offset, u32 *val);
185 int offset, u32 *val);
237 int offset, u32 *val);
239 int offset, u32 *val);
241 u64 id, u64 *val);
245 u32 intid, u64 *val);
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| D | vgic-its.c | 502 u32 val; in vgic_mmio_read_its_iidr() local
504 val = (its->abi_rev << GITS_IIDR_REV_SHIFT) & GITS_IIDR_REV_MASK; in vgic_mmio_read_its_iidr()
505 val |= (PRODUCT_ID_KVM << GITS_IIDR_PRODUCTID_SHIFT) | IMPLEMENTER_ARM; in vgic_mmio_read_its_iidr()
506 return val; in vgic_mmio_read_its_iidr()
512 unsigned long val) in vgic_mmio_uaccess_write_its_iidr() argument
514 u32 rev = GITS_IIDR_REV(val); in vgic_mmio_uaccess_write_its_iidr()
1505 unsigned long val) in vgic_mmio_write_its_cbaser() argument
1512 its->cbaser = update_64bit_reg(its->cbaser, addr & 7, len, val); in vgic_mmio_write_its_cbaser()
1566 unsigned long val) in vgic_mmio_write_its_cwriter() argument
1575 reg = update_64bit_reg(its->cwriter, addr & 7, len, val); in vgic_mmio_write_its_cwriter()
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| D | vgic-kvm-device.c | 174 u32 val; in vgic_set_common_attr() local
177 if (get_user(val, uaddr)) in vgic_set_common_attr()
186 if (val < (VGIC_NR_PRIVATE_IRQS + 32) || in vgic_set_common_attr()
187 val > VGIC_MAX_RESERVED || in vgic_set_common_attr()
188 (val & 31)) in vgic_set_common_attr()
197 val - VGIC_NR_PRIVATE_IRQS; in vgic_set_common_attr()
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| /virt/kvm/ |
| D | kvm_main.c | 2464 unsigned int old, val, grow, grow_start; in grow_halt_poll_ns() local
2466 old = val = vcpu->halt_poll_ns; in grow_halt_poll_ns()
2472 val *= grow; in grow_halt_poll_ns()
2473 if (val < grow_start) in grow_halt_poll_ns()
2474 val = grow_start; in grow_halt_poll_ns()
2476 if (val > halt_poll_ns) in grow_halt_poll_ns()
2477 val = halt_poll_ns; in grow_halt_poll_ns()
2479 vcpu->halt_poll_ns = val; in grow_halt_poll_ns()
2481 trace_kvm_halt_poll_ns_grow(vcpu->vcpu_id, val, old); in grow_halt_poll_ns()
2486 unsigned int old, val, shrink, grow_start; in shrink_halt_poll_ns() local
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| D | eventfd.c | 683 ioeventfd_in_range(struct _ioeventfd *p, gpa_t addr, int len, const void *val) in ioeventfd_in_range() argument
705 BUG_ON(!IS_ALIGNED((unsigned long)val, len)); in ioeventfd_in_range()
709 _val = *(u8 *)val; in ioeventfd_in_range()
712 _val = *(u16 *)val; in ioeventfd_in_range()
715 _val = *(u32 *)val; in ioeventfd_in_range()
718 _val = *(u64 *)val; in ioeventfd_in_range()
730 int len, const void *val) in ioeventfd_write() argument
734 if (!ioeventfd_in_range(p, addr, len, val)) in ioeventfd_write()
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| D | coalesced_mmio.c | 66 int len, const void *val) in coalesced_mmio_write() argument
88 memcpy(ring->coalesced_mmio[insert].data, val, len); in coalesced_mmio_write()
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