Searched +full:reg +full:- +full:shift (Results 1 – 25 of 71) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | gate.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 quite much similar to the basic gate-clock [2], however,
9 will be controlled instead and the corresponding hw-ops for
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
17 - compatible : shall be one of:
18 "ti,gate-clock" - basic gate clock
19 "ti,wait-gate-clock" - gate clock which waits until clock is active before
21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
22 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
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| D | mux.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped multiplexer with multiple input clock signals or
24 "index-starts-at-one" modified the scheme as follows:
32 the number of bits to shift the control field in the register can be
33 supplied. If the shift value is missing it is the same as supplying
34 a zero shift.
36 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
39 - compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
40 - #clock-cells : from common clock binding; shall be set to 0.
41 - clocks : link phandles of parent clocks
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| D | apll.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped APLL with usually two selectable input clocks
13 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
18 - #clock-cells : from common clock binding; shall be set to 0.
19 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
20 - reg : address and length of the register set for controlling the APLL.
22 "control" - contains the control register offset
23 "idlest" - contains the idlest register offset
24 "autoidle" - contains the autoidle register offset (OMAP2 only)
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| D | divider.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped adjustable clock rate divider that does not gate and has
17 ti,index-starts-at-one - valid divisor values start at 1, not the default
24 ti,index-power-of-two - valid divisor values are powers of two. E.g:
41 Any zero value in this array means the corresponding bit-value is invalid
46 the number of bits to shift that mask, if necessary. If the shift value
47 is missing it is the same as supplying a zero shift.
52 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
56 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
57 - #clock-cells : from common clock binding; shall be set to 0.
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| D | interface.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 quite much similar to the basic gate-clock [2], however,
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
15 - compatible : shall be one of:
16 "ti,omap3-interface-clock" - basic OMAP3 interface clock
17 "ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
19 "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
21 "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
22 "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
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| D | autoidle.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
9 or fixed-factor.
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - reg : offset for the register controlling the autoidle
15 - ti,autoidle-shift : bit shift of the autoidle enable bit
16 - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
20 #clock-cells = <0>;
21 compatible = "ti,divider-clock";
23 ti,max-div = <31>;
24 ti,autoidle-shift = <8>;
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| D | fixed-factor-clock.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible : shall be "ti,fixed-factor-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - ti,clock-div: fixed divider.
15 - ti,clock-mult: fixed multiplier.
16 - clocks: parent clock.
19 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
21 - reg: offset for the autoidle register of this clock, see [2]
22 - ti,invert-autoidle-bit: autoidle is enabled by setting the bit to 0, see [2]
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| D | composite.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped composite clock with multiple different sub-types;
18 "ti,*composite*-clock" types.
20 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
26 - compatible : shall be: "ti,composite-clock"
27 - clocks : link phandles of component clocks
28 - #clock-cells : from common clock binding; shall be set to 0.
33 #clock-cells = <0>;
34 compatible = "ti,composite-interface-clock";
36 ti,bit-shift = <5>;
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| /Documentation/devicetree/bindings/clock/ |
| D | keystone-pll.txt | 1 Status: Unstable - ABI compatibility may be broken in the future
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - #clock-cells : from common clock binding; shall be set to 0.
15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
16 - clocks : parent clock phandle
17 - reg - pll control0 and pll multipler registers
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
25 #clock-cells = <0>;
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| D | xgene.txt | 1 Device Tree Clock bindings for APM X-Gene
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
17 - reg : shall be the physical PLL register address for the pll clock.
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| /Documentation/devicetree/bindings/regulator/ |
| D | anatop-regulator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13 - $ref: "regulator.yaml#"
17 const: fsl,anatop-regulator
19 regulator-name: true
21 anatop-reg-offset:
25 anatop-vol-bit-shift:
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| D | max8973-regulator.txt | 5 - compatible: must be one of following:
8 - reg: the i2c slave address of the regulator. It should be 0x1b.
15 -maxim,externally-enable: boolean, externally control the regulator output
17 -maxim,enable-gpio: GPIO for enable control. If the valid GPIO is provided
19 -maxim,dvs-gpio: GPIO which is connected to DVS pin of device.
20 -maxim,dvs-default-state: Default state of GPIO during initialisation.
22 -maxim,enable-remote-sense: boolean, enable reote sense.
23 -maxim,enable-falling-slew-rate: boolean, enable falling slew rate.
24 -maxim,enable-active-discharge: boolean: enable active discharge.
25 -maxim,enable-frequency-shift: boolean, enable 9% frequency shift.
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| /Documentation/arm/samsung/ |
| D | clksrc-change-registers.awk | 1 #!/usr/bin/awk -f
3 # Copyright 2010 Ben Dooks <ben-linux@fluff.org>
8 # ./clksrc-change-registers.awk arch/arm/plat-s5pc1xx/include/plat/regs-clock.h < src > dst
14 return substr(s, eqat+2, (comat-eqat)-2)
19 return substr(b, 2, length(b)-2)
52 printf "cannot find shift " s "\n" > "/dev/stderr"
79 printf "=> '" name "' LENGTH=" dmask[name,0] " SHIFT=" dmask[name,1] "\n" > "/dev/stderr"
88 shift=""
103 if (line ~ /\.shift/) {
104 shift = extract_value(line)
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-stp-xway.txt | 4 peripheral controller used to drive external shift register cascades. At most
10 - compatible : Should be "lantiq,gpio-stp-xway"
11 - reg : Address and length of the register set for the device
12 - #gpio-cells : Should be two. The first cell is the pin number and
15 - gpio-controller : Marks the device node as a gpio controller.
18 - lantiq,shadow : The default value that we shall assume as already set on the
19 shift register cascade.
20 - lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled
21 in the shift register cascade.
22 - lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
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| D | gpio-pisosr.txt | 1 Generic Parallel-in/Serial-out Shift Register GPIO Driver
3 This binding describes generic parallel-in/serial-out shift register
5 SN74165 serial-out shift registers and the SN65HVS88x series of
9 - compatible : Should be "pisosr-gpio".
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - #gpio-cells : Should be two. For consumer use see gpio.txt.
14 - ngpios : Number of used GPIO lines (0..n-1), default is 8.
15 - load-gpios : GPIO pin specifier attached to load enable, this
20 nodes please refer to ../spi/spi-bus.txt.
25 compatible = "ti,sn65hvs882", "pisosr-gpio";
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| D | gpio-74x164.txt | 1 * Generic 8-bits shift register GPIO driver
4 - compatible: Should contain one of the following:
7 - reg : chip select number
8 - gpio-controller : Marks the device node as a gpio controller.
9 - #gpio-cells : Should be two. The first cell is the pin number and
13 - registers-number: Number of daisy-chained shift registers
16 - enable-gpios: GPIO connected to the OE (Output Enable) pin.
22 reg = <0>;
23 gpio-controller;
24 #gpio-cells = <2>;
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| D | spear_spics.txt | 17 * compatible: should be defined as "st,spear-spics-gpio"
18 * reg: mentioning address range of spics controller
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
30 -------
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| /Documentation/devicetree/bindings/mmc/ |
| D | exynos-dw-mshc.txt | 7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-ocores.txt | 1 Device tree configuration for i2c-ocores
4 - compatible : "opencores,i2c-ocores"
6 "sifive,fu540-c000-i2c", "sifive,i2c0"
8 FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
10 - reg : bus address start and address range size of device
11 - clocks : handle to the controller clock; see the note below.
12 Mutually exclusive with opencores,ip-clock-frequency
13 - opencores,ip-clock-frequency: frequency of the controller clock in Hz;
15 - #address-cells : should be <1>
16 - #size-cells : should be <0>
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-samsung.txt | 8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
18 - interrupts: The interrupt number to the cpu. The interrupt specifier format
21 - dmas : Two or more DMA channel specifiers following the convention outlined
24 - dma-names: Names for the dma channels. There must be at least one channel
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| /Documentation/devicetree/bindings/serial/ |
| D | 8250.yaml | 3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: /schemas/serial.yaml#
14 - if:
16 - aspeed,sirq-polarity-sense
20 const: aspeed,ast2500-vuart
21 - if:
24 const: mrvl,mmp-uart
27 reg-shift:
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| D | snps-dw-apb-uart.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a06g032-uart
21 - renesas,r9a06g033-uart
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| /Documentation/devicetree/bindings/net/ |
| D | socfpga-dwmac.txt | 9 - compatible : For Cyclone5/Arria5 SoCs it should contain
10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
11 "altr,socfpga-stmmac-a10-s10".
14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
15 encompasses the glue register, the register offset, and the register shift.
16 On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
17 on the Arria10/Stratix10/Agilex platforms, the register shift represents
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
24 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
26 phy-mode: The phy mode the ethernet operates in
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| D | smsc911x.txt | 1 * Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
4 - compatible : Should be "smsc,lan<model>", "smsc,lan9115"
5 - reg : Address and length of the io space for SMSC LAN
6 - interrupts : one or two interrupt specifiers
7 - The first interrupt is the SMSC LAN interrupt line
8 - The second interrupt (if present) is the PME (power
11 - phy-mode : See ethernet.txt file in the same directory
14 - reg-shift : Specify the quantity to shift the register offsets by
15 - reg-io-width : Specify the size (in bytes) of the IO accesses that
18 - smsc,irq-active-high : Indicates the IRQ polarity is active-high
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| /Documentation/devicetree/bindings/ipmi/ |
| D | ipmi-smic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ipmi/ipmi-smic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Corey Minyard <cminyard@mvista.com>
17 - ipmi-kcs
18 - ipmi-smic
19 - ipmi-bt
23 - const: "ipmi"
25 reg:
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