| /drivers/gpu/drm/amd/amdgpu/ |
| D | nv.c | 181 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, in nv_query_video_codecs() argument
184 switch (adev->asic_type) { in nv_query_video_codecs()
186 if (amdgpu_sriov_vf(adev)) { in nv_query_video_codecs()
234 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg() argument
237 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg()
238 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg()
240 return amdgpu_device_indirect_rreg(adev, address, data, reg); in nv_pcie_rreg()
243 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_pcie_wreg() argument
247 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg()
248 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg()
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| D | soc15.c | 154 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, in soc15_query_video_codecs() argument
157 switch (adev->asic_type) { in soc15_query_video_codecs()
188 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg() argument
191 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg()
192 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg()
194 return amdgpu_device_indirect_rreg(adev, address, data, reg); in soc15_pcie_rreg()
197 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_pcie_wreg() argument
201 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg()
202 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg()
204 amdgpu_device_indirect_wreg(adev, address, data, reg, v); in soc15_pcie_wreg()
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| D | amdgpu_device.c | 152 struct amdgpu_device *adev = drm_to_adev(ddev); in amdgpu_device_get_pcie_replay_count() local
153 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); in amdgpu_device_get_pcie_replay_count()
161 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
177 struct amdgpu_device *adev = drm_to_adev(ddev); in amdgpu_device_get_product_name() local
179 return sysfs_emit(buf, "%s\n", adev->product_name); in amdgpu_device_get_product_name()
199 struct amdgpu_device *adev = drm_to_adev(ddev); in amdgpu_device_get_product_number() local
201 return sysfs_emit(buf, "%s\n", adev->product_number); in amdgpu_device_get_product_number()
221 struct amdgpu_device *adev = drm_to_adev(ddev); in amdgpu_device_get_serial_number() local
223 return sysfs_emit(buf, "%s\n", adev->serial); in amdgpu_device_get_serial_number()
239 struct amdgpu_device *adev = drm_to_adev(dev); in amdgpu_device_supports_px() local
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| D | gmc_v9_0.c | 412 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, in gmc_v9_0_ecc_interrupt_state() argument
421 if (adev->asic_type >= CHIP_VEGA20) in gmc_v9_0_ecc_interrupt_state()
462 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, in gmc_v9_0_vm_fault_interrupt_state() argument
480 for (j = 0; j < adev->num_vmhubs; j++) { in gmc_v9_0_vm_fault_interrupt_state()
481 hub = &adev->vmhub[j]; in gmc_v9_0_vm_fault_interrupt_state()
491 for (j = 0; j < adev->num_vmhubs; j++) { in gmc_v9_0_vm_fault_interrupt_state()
492 hub = &adev->vmhub[j]; in gmc_v9_0_vm_fault_interrupt_state()
508 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, in gmc_v9_0_process_interrupt() argument
528 if (entry->ih != &adev->irq.ih_soft && in gmc_v9_0_process_interrupt()
529 amdgpu_gmc_filter_faults(adev, addr, entry->pasid, in gmc_v9_0_process_interrupt()
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| D | gmc_v10_0.c | 58 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, in gmc_v10_0_ecc_interrupt_state() argument
67 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, in gmc_v10_0_vm_fault_interrupt_state() argument
74 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); in gmc_v10_0_vm_fault_interrupt_state()
76 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); in gmc_v10_0_vm_fault_interrupt_state()
80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); in gmc_v10_0_vm_fault_interrupt_state()
82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); in gmc_v10_0_vm_fault_interrupt_state()
91 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, in gmc_v10_0_process_interrupt() argument
97 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; in gmc_v10_0_process_interrupt()
109 if (entry->ih != &adev->irq.ih_soft && in gmc_v10_0_process_interrupt()
110 amdgpu_gmc_filter_faults(adev, addr, entry->pasid, in gmc_v10_0_process_interrupt()
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| D | amdgpu_gfx.c | 40 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, in amdgpu_gfx_mec_queue_to_bit() argument
45 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
46 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
47 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
53 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, in amdgpu_queue_mask_bit_to_mec_queue() argument
56 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
57 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
58 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
59 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
60 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
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| D | amdgpu_virt.c | 41 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) in amdgpu_virt_mmio_blocked() argument
49 void amdgpu_virt_init_setting(struct amdgpu_device *adev) in amdgpu_virt_init_setting() argument
51 struct drm_device *ddev = adev_to_drm(adev); in amdgpu_virt_init_setting()
54 if (adev->asic_type != CHIP_ALDEBARAN && in amdgpu_virt_init_setting()
55 adev->asic_type != CHIP_ARCTURUS) { in amdgpu_virt_init_setting()
56 if (adev->mode_info.num_crtc == 0) in amdgpu_virt_init_setting()
57 adev->mode_info.num_crtc = 1; in amdgpu_virt_init_setting()
58 adev->enable_virtual_display = true; in amdgpu_virt_init_setting()
61 adev->cg_flags = 0; in amdgpu_virt_init_setting()
62 adev->pg_flags = 0; in amdgpu_virt_init_setting()
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| D | amdgpu_ras.c | 86 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
89 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) in amdgpu_ras_set_error_query_ready() argument
91 if (adev && amdgpu_ras_get_context(adev)) in amdgpu_ras_set_error_query_ready()
92 amdgpu_ras_get_context(adev)->error_query_ready = ready; in amdgpu_ras_set_error_query_ready()
95 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) in amdgpu_ras_get_error_query_ready() argument
97 if (adev && amdgpu_ras_get_context(adev)) in amdgpu_ras_get_error_query_ready()
98 return amdgpu_ras_get_context(adev)->error_query_ready; in amdgpu_ras_get_error_query_ready()
103 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address) in amdgpu_reserve_page_direct() argument
108 if ((address >= adev->gmc.mc_vram_size) || in amdgpu_reserve_page_direct()
110 dev_warn(adev->dev, in amdgpu_reserve_page_direct()
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| D | vi.c | 257 static int vi_query_video_codecs(struct amdgpu_device *adev, bool encode, in vi_query_video_codecs() argument
260 switch (adev->asic_type) { in vi_query_video_codecs()
298 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) in vi_pcie_rreg() argument
303 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
307 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
311 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_pcie_wreg() argument
315 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
320 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
323 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) in vi_smc_rreg() argument
328 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_smc_rreg()
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| D | amdgpu_irq.c | 121 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, in amdgpu_hotplug_work_func() local
123 struct drm_device *dev = adev_to_drm(adev); in amdgpu_hotplug_work_func()
145 void amdgpu_irq_disable_all(struct amdgpu_device *adev) in amdgpu_irq_disable_all() argument
151 spin_lock_irqsave(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
153 if (!adev->irq.client[i].sources) in amdgpu_irq_disable_all()
157 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; in amdgpu_irq_disable_all()
164 r = src->funcs->set(adev, src, k, in amdgpu_irq_disable_all()
172 spin_unlock_irqrestore(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
189 struct amdgpu_device *adev = drm_to_adev(dev); in amdgpu_irq_handler() local
192 ret = amdgpu_ih_process(adev, &adev->irq.ih); in amdgpu_irq_handler()
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| D | amdgpu_acp.c | 98 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in acp_sw_init() local
100 adev->acp.parent = adev->dev; in acp_sw_init()
102 adev->acp.cgs_device = in acp_sw_init()
103 amdgpu_cgs_create_device(adev); in acp_sw_init()
104 if (!adev->acp.cgs_device) in acp_sw_init()
112 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in acp_sw_fini() local
114 if (adev->acp.cgs_device) in acp_sw_fini()
115 amdgpu_cgs_destroy_device(adev->acp.cgs_device); in acp_sw_fini()
121 void *adev; member
128 struct amdgpu_device *adev; in acp_poweroff() local
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| D | amdgpu_debugfs.c | 71 struct amdgpu_device *adev = file_inode(f)->i_private; in amdgpu_debugfs_process_reg_op() local
113 r = pm_runtime_get_sync(adev_to_drm(adev)->dev); in amdgpu_debugfs_process_reg_op()
115 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); in amdgpu_debugfs_process_reg_op()
119 r = amdgpu_virt_enable_access_debugfs(adev); in amdgpu_debugfs_process_reg_op()
121 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); in amdgpu_debugfs_process_reg_op()
126 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
127 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_process_reg_op()
128 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); in amdgpu_debugfs_process_reg_op()
129 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); in amdgpu_debugfs_process_reg_op()
130 amdgpu_virt_disable_access_debugfs(adev); in amdgpu_debugfs_process_reg_op()
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| D | amdgpu_rlc.c | 37 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev) in amdgpu_gfx_rlc_enter_safe_mode() argument
39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
43 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
46 if (adev->cg_flags & in amdgpu_gfx_rlc_enter_safe_mode()
49 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
61 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev) in amdgpu_gfx_rlc_exit_safe_mode() argument
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
67 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
70 if (adev->cg_flags & in amdgpu_gfx_rlc_exit_safe_mode()
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| D | gmc_v6_0.c | 44 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
45 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
64 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) in gmc_v6_0_mc_stop() argument
68 gmc_v6_0_wait_for_idle((void *)adev); in gmc_v6_0_mc_stop()
84 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev) in gmc_v6_0_mc_resume() argument
98 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) in gmc_v6_0_init_microcode() argument
107 switch (adev->asic_type) { in gmc_v6_0_init_microcode()
134 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v6_0_init_microcode()
138 err = amdgpu_ucode_validate(adev->gmc.fw); in gmc_v6_0_init_microcode()
142 dev_err(adev->dev, in gmc_v6_0_init_microcode()
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| D | amdgpu_bios.c | 91 static bool igp_read_bios_from_vram(struct amdgpu_device *adev) in igp_read_bios_from_vram() argument
97 if (!(adev->flags & AMD_IS_APU)) in igp_read_bios_from_vram()
98 if (amdgpu_device_need_post(adev)) in igp_read_bios_from_vram()
102 if (pci_resource_len(adev->pdev, 0) == 0) in igp_read_bios_from_vram()
105 adev->bios = NULL; in igp_read_bios_from_vram()
106 vram_base = pci_resource_start(adev->pdev, 0); in igp_read_bios_from_vram()
112 adev->bios = kmalloc(size, GFP_KERNEL); in igp_read_bios_from_vram()
113 if (!adev->bios) { in igp_read_bios_from_vram()
117 adev->bios_size = size; in igp_read_bios_from_vram()
118 memcpy_fromio(adev->bios, bios, size); in igp_read_bios_from_vram()
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| D | amdgpu_gart.c | 72 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) in amdgpu_gart_dummy_page_init() argument
76 if (adev->dummy_page_addr) in amdgpu_gart_dummy_page_init()
78 adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0, in amdgpu_gart_dummy_page_init()
80 if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) { in amdgpu_gart_dummy_page_init()
81 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); in amdgpu_gart_dummy_page_init()
82 adev->dummy_page_addr = 0; in amdgpu_gart_dummy_page_init()
95 void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) in amdgpu_gart_dummy_page_fini() argument
97 if (!adev->dummy_page_addr) in amdgpu_gart_dummy_page_fini()
99 dma_unmap_page(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE, in amdgpu_gart_dummy_page_fini()
101 adev->dummy_page_addr = 0; in amdgpu_gart_dummy_page_fini()
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| D | amdgpu_gmc.c | 44 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev) in amdgpu_gmc_pdb0_alloc() argument
48 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; in amdgpu_gmc_pdb0_alloc()
49 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21; in amdgpu_gmc_pdb0_alloc()
62 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
66 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false); in amdgpu_gmc_pdb0_alloc()
70 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM); in amdgpu_gmc_pdb0_alloc()
73 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0); in amdgpu_gmc_pdb0_alloc()
77 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
81 amdgpu_bo_unpin(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
83 amdgpu_bo_unreserve(adev->gmc.pdb0_bo); in amdgpu_gmc_pdb0_alloc()
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| D | amdgpu_amdkfd.c | 66 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) in amdgpu_amdkfd_device_probe() argument
68 bool vf = amdgpu_sriov_vf(adev); in amdgpu_amdkfd_device_probe()
73 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, in amdgpu_amdkfd_device_probe()
74 adev->pdev, adev->asic_type, vf); in amdgpu_amdkfd_device_probe()
76 if (adev->kfd.dev) in amdgpu_amdkfd_device_probe()
77 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; in amdgpu_amdkfd_device_probe()
93 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, in amdgpu_doorbell_get_kfd_info() argument
102 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { in amdgpu_doorbell_get_kfd_info()
103 *aperture_base = adev->doorbell.base; in amdgpu_doorbell_get_kfd_info()
104 *aperture_size = adev->doorbell.size; in amdgpu_doorbell_get_kfd_info()
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| D | mxgpu_nv.c | 34 static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev) in xgpu_nv_mailbox_send_ack() argument
39 static void xgpu_nv_mailbox_set_valid(struct amdgpu_device *adev, bool val) in xgpu_nv_mailbox_set_valid() argument
53 static enum idh_event xgpu_nv_mailbox_peek_msg(struct amdgpu_device *adev) in xgpu_nv_mailbox_peek_msg() argument
59 static int xgpu_nv_mailbox_rcv_msg(struct amdgpu_device *adev, in xgpu_nv_mailbox_rcv_msg() argument
68 xgpu_nv_mailbox_send_ack(adev); in xgpu_nv_mailbox_rcv_msg()
73 static uint8_t xgpu_nv_peek_ack(struct amdgpu_device *adev) in xgpu_nv_peek_ack() argument
78 static int xgpu_nv_poll_ack(struct amdgpu_device *adev) in xgpu_nv_poll_ack() argument
97 static int xgpu_nv_poll_msg(struct amdgpu_device *adev, enum idh_event event) in xgpu_nv_poll_msg() argument
106 r = xgpu_nv_mailbox_rcv_msg(adev, event); in xgpu_nv_poll_msg()
118 static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev, in xgpu_nv_mailbox_trans_msg() argument
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| D | amdgpu.h | 117 struct amdgpu_device *adev; member
326 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
328 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
330 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
359 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
364 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
367 int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
373 bool amdgpu_get_bios(struct amdgpu_device *adev);
374 bool amdgpu_read_bios(struct amdgpu_device *adev);
454 struct amdgpu_device *adev; member
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| D | amdgpu_kms.c | 46 static void amdgpu_runtime_pm_quirk(struct amdgpu_device *adev) in amdgpu_runtime_pm_quirk() argument
52 if (((adev->pdev->device == 0x73A1) && (adev->pdev->revision == 0x00)) || in amdgpu_runtime_pm_quirk()
53 ((adev->pdev->device == 0x73BF) && (adev->pdev->revision == 0xCF))) in amdgpu_runtime_pm_quirk()
54 adev->runpm = false; in amdgpu_runtime_pm_quirk()
57 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) in amdgpu_unregister_gpu_instance() argument
66 if (gpu_instance->adev == adev) { in amdgpu_unregister_gpu_instance()
70 if (adev->flags & AMD_IS_APU) in amdgpu_unregister_gpu_instance()
91 struct amdgpu_device *adev = drm_to_adev(dev); in amdgpu_driver_unload_kms() local
93 if (adev == NULL) in amdgpu_driver_unload_kms()
96 amdgpu_unregister_gpu_instance(adev); in amdgpu_driver_unload_kms()
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| /drivers/gpu/drm/amd/pm/inc/ |
| D | amdgpu_dpm.h | 256 #define amdgpu_dpm_pre_set_power_state(adev) \ argument
257 ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
259 #define amdgpu_dpm_set_power_state(adev) \ argument
260 ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
262 #define amdgpu_dpm_post_set_power_state(adev) \ argument
263 ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
265 #define amdgpu_dpm_display_configuration_changed(adev) \ argument
266 ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
268 #define amdgpu_dpm_print_power_state(adev, ps) \ argument
269 ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
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| /drivers/gpu/drm/amd/pm/powerplay/ |
| D | kv_dpm.c | 46 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
47 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
49 static void kv_init_graphics_levels(struct amdgpu_device *adev);
50 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
51 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
52 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
53 static void kv_enable_new_levels(struct amdgpu_device *adev);
54 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
56 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
57 static int kv_set_enabled_levels(struct amdgpu_device *adev);
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| /drivers/gpu/drm/amd/pm/ |
| D | amdgpu_dpm.c | 110 void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, in amdgpu_dpm_print_ps_status() argument
114 if (rps == adev->pm.dpm.current_ps) in amdgpu_dpm_print_ps_status()
116 if (rps == adev->pm.dpm.requested_ps) in amdgpu_dpm_print_ps_status()
118 if (rps == adev->pm.dpm.boot_ps) in amdgpu_dpm_print_ps_status()
123 void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev) in amdgpu_dpm_get_active_displays() argument
125 struct drm_device *ddev = adev_to_drm(adev); in amdgpu_dpm_get_active_displays()
129 adev->pm.dpm.new_active_crtcs = 0; in amdgpu_dpm_get_active_displays()
130 adev->pm.dpm.new_active_crtc_count = 0; in amdgpu_dpm_get_active_displays()
131 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { in amdgpu_dpm_get_active_displays()
136 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id); in amdgpu_dpm_get_active_displays()
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| D | amdgpu_pm.c | 124 struct amdgpu_device *adev = drm_to_adev(ddev); in amdgpu_get_power_dpm_state() local
125 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_get_power_dpm_state()
129 if (amdgpu_in_reset(adev)) in amdgpu_get_power_dpm_state()
131 if (adev->in_suspend && !adev->in_runpm) in amdgpu_get_power_dpm_state()
141 pm = amdgpu_dpm_get_current_power_state(adev); in amdgpu_get_power_dpm_state()
143 pm = adev->pm.dpm.user_state; in amdgpu_get_power_dpm_state()
160 struct amdgpu_device *adev = drm_to_adev(ddev); in amdgpu_set_power_dpm_state() local
164 if (amdgpu_in_reset(adev)) in amdgpu_set_power_dpm_state()
166 if (adev->in_suspend && !adev->in_runpm) in amdgpu_set_power_dpm_state()
184 if (is_support_sw_smu(adev)) { in amdgpu_set_power_dpm_state()
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