| /drivers/target/iscsi/ |
| D | iscsi_target_erl2.c | 78 struct iscsi_conn_recovery *cr) in iscsit_attach_active_connection_recovery_entry() argument
81 list_add_tail(&cr->cr_list, &sess->cr_active_list); in iscsit_attach_active_connection_recovery_entry()
89 struct iscsi_conn_recovery *cr) in iscsit_attach_inactive_connection_recovery_entry() argument
92 list_add_tail(&cr->cr_list, &sess->cr_inactive_list); in iscsit_attach_inactive_connection_recovery_entry()
106 struct iscsi_conn_recovery *cr; in iscsit_get_inactive_connection_recovery_entry() local
109 list_for_each_entry(cr, &sess->cr_inactive_list, cr_list) { in iscsit_get_inactive_connection_recovery_entry()
110 if (cr->cid == cid) { in iscsit_get_inactive_connection_recovery_entry()
112 return cr; in iscsit_get_inactive_connection_recovery_entry()
123 struct iscsi_conn_recovery *cr, *cr_tmp; in iscsit_free_connection_recovery_entries() local
126 list_for_each_entry_safe(cr, cr_tmp, &sess->cr_active_list, cr_list) { in iscsit_free_connection_recovery_entries()
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| D | iscsi_target_tmr.c | 111 struct iscsi_conn_recovery *cr = NULL; in iscsit_tmr_task_reassign() local
127 ret = iscsit_find_cmd_for_recovery(conn->sess, &ref_cmd, &cr, hdr->rtt); in iscsit_tmr_task_reassign()
130 " %hu\n", ref_cmd->init_task_tag, cr->cid); in iscsit_tmr_task_reassign()
141 if (cr->maxrecvdatasegmentlength != in iscsit_tmr_task_reassign()
148 if (cr->maxxmitdatasegmentlength != in iscsit_tmr_task_reassign()
167 tmr_req->conn_recovery = cr; in iscsit_tmr_task_reassign()
179 struct iscsi_conn_recovery *cr, in iscsit_task_reassign_remove_cmd() argument
184 spin_lock(&cr->conn_recovery_cmd_lock); in iscsit_task_reassign_remove_cmd()
186 spin_unlock(&cr->conn_recovery_cmd_lock); in iscsit_task_reassign_remove_cmd()
189 " %hu on SID: %u\n", cr->cid, sess->sid); in iscsit_task_reassign_remove_cmd()
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| /drivers/crypto/ccp/ |
| D | ccp-dev-v3.c | 74 static int ccp_do_cmd(struct ccp_op *op, u32 *cr, unsigned int cr_count) in ccp_do_cmd() argument
107 iowrite32(*(cr + i), cr_addr); in ccp_do_cmd()
150 u32 cr[6]; in ccp_perform_aes() local
153 cr[0] = (CCP_ENGINE_AES << REQ1_ENGINE_SHIFT) in ccp_perform_aes()
158 cr[1] = op->src.u.dma.length - 1; in ccp_perform_aes()
159 cr[2] = ccp_addr_lo(&op->src.u.dma); in ccp_perform_aes()
160 cr[3] = (op->sb_ctx << REQ4_KSB_SHIFT) in ccp_perform_aes()
163 cr[4] = ccp_addr_lo(&op->dst.u.dma); in ccp_perform_aes()
164 cr[5] = (CCP_MEMTYPE_SYSTEM << REQ6_MEMTYPE_SHIFT) in ccp_perform_aes()
168 cr[0] |= ((0x7f) << REQ1_AES_CFB_SIZE_SHIFT); in ccp_perform_aes()
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| /drivers/misc/cxl/ |
| D | sysfs.c | 508 int cr; member
519 struct afu_config_record *cr = to_cr(kobj); in vendor_show() local
521 return scnprintf(buf, PAGE_SIZE, "0x%.4x\n", cr->vendor); in vendor_show()
527 struct afu_config_record *cr = to_cr(kobj); in device_show() local
529 return scnprintf(buf, PAGE_SIZE, "0x%.4x\n", cr->device); in device_show()
535 struct afu_config_record *cr = to_cr(kobj); in class_show() local
537 return scnprintf(buf, PAGE_SIZE, "0x%.6x\n", cr->class); in class_show()
544 struct afu_config_record *cr = to_cr(kobj); in afu_read_config() local
550 rc = cxl_ops->afu_cr_read64(afu, cr->cr, off & ~0x7, &val); in afu_read_config()
576 struct afu_config_record *cr = to_cr(kobj); in release_afu_config_record() local
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| /drivers/clocksource/ |
| D | timer-fttmr010.c | 146 u32 cr; in fttmr010_timer_set_next_event() local
159 cr = readl(fttmr010->base + TIMER1_COUNT); in fttmr010_timer_set_next_event()
160 writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); in fttmr010_timer_set_next_event()
164 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
165 cr |= fttmr010->t1_enable_val; in fttmr010_timer_set_next_event()
166 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
184 u32 cr; in fttmr010_timer_shutdown() local
187 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_shutdown()
188 cr &= ~fttmr010->t1_enable_val; in fttmr010_timer_shutdown()
189 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_shutdown()
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| /drivers/i2c/busses/ |
| D | i2c-iop3xx.c | 67 u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE; in iop3xx_i2c_enable() local
86 cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE | in iop3xx_i2c_enable()
89 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_enable()
95 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_transaction_cleanup() local
97 cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | in iop3xx_i2c_transaction_cleanup()
100 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_transaction_cleanup()
233 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_send_target_addr() local
246 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK); in iop3xx_i2c_send_target_addr()
247 cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE; in iop3xx_i2c_send_target_addr()
249 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_send_target_addr()
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| /drivers/media/test-drivers/vicodec/ |
| D | codec-v4l2-fwht.c | 113 rf->cr = NULL; in prepare_raw_frame()
120 rf->cr = NULL; in prepare_raw_frame()
124 rf->cr = rf->cb + size / 4; in prepare_raw_frame()
127 rf->cr = rf->luma + size; in prepare_raw_frame()
128 rf->cb = rf->cr + size / 4; in prepare_raw_frame()
132 rf->cr = rf->cb + size / 2; in prepare_raw_frame()
138 rf->cr = rf->cb + 1; in prepare_raw_frame()
143 rf->cr = rf->luma + size; in prepare_raw_frame()
144 rf->cb = rf->cr + 1; in prepare_raw_frame()
148 rf->cr = rf->cb + 2; in prepare_raw_frame()
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| /drivers/net/ethernet/ni/ |
| D | nixge.c | 288 u32 cr; in nixge_hw_dma_bd_init() local
344 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_hw_dma_bd_init()
346 cr = ((cr & ~XAXIDMA_COALESCE_MASK) | in nixge_hw_dma_bd_init()
349 cr = ((cr & ~XAXIDMA_DELAY_MASK) | in nixge_hw_dma_bd_init()
352 cr |= XAXIDMA_IRQ_ALL_MASK; in nixge_hw_dma_bd_init()
354 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr); in nixge_hw_dma_bd_init()
357 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_hw_dma_bd_init()
359 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) | in nixge_hw_dma_bd_init()
362 cr = (((cr & ~XAXIDMA_DELAY_MASK)) | in nixge_hw_dma_bd_init()
365 cr |= XAXIDMA_IRQ_ALL_MASK; in nixge_hw_dma_bd_init()
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| /drivers/gpu/drm/mcde/ |
| D | mcde_clk_div.c | 12 u32 cr; member
23 val = readl(mcde->regs + cdiv->cr); in mcde_clk_div_enable()
37 writel(val, mcde->regs + cdiv->cr); in mcde_clk_div_enable()
86 u32 cr; in mcde_clk_div_recalc_rate() local
97 cr = readl(mcde->regs + cdiv->cr); in mcde_clk_div_recalc_rate()
98 if (cr & MCDE_CRX1_BCD) in mcde_clk_div_recalc_rate()
102 div = cr & MCDE_CRX1_PCD_MASK; in mcde_clk_div_recalc_rate()
113 u32 cr = 0; in mcde_clk_div_set_rate() local
121 cr |= MCDE_CRX1_BCD; in mcde_clk_div_set_rate()
124 cr |= div & MCDE_CRX1_PCD_MASK; in mcde_clk_div_set_rate()
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| D | mcde_display.c | 200 u32 cr; in mcde_configure_extsrc() local
205 cr = MCDE_EXTSRC0CR; in mcde_configure_extsrc()
209 cr = MCDE_EXTSRC1CR; in mcde_configure_extsrc()
213 cr = MCDE_EXTSRC2CR; in mcde_configure_extsrc()
217 cr = MCDE_EXTSRC3CR; in mcde_configure_extsrc()
221 cr = MCDE_EXTSRC4CR; in mcde_configure_extsrc()
225 cr = MCDE_EXTSRC5CR; in mcde_configure_extsrc()
229 cr = MCDE_EXTSRC6CR; in mcde_configure_extsrc()
233 cr = MCDE_EXTSRC7CR; in mcde_configure_extsrc()
237 cr = MCDE_EXTSRC8CR; in mcde_configure_extsrc()
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| /drivers/rtc/ |
| D | rtc-ds1374.c | 190 int cr, sr; in ds1374_read_alarm() local
198 cr = ret = i2c_smbus_read_byte_data(client, DS1374_REG_CR); in ds1374_read_alarm()
215 alarm->enabled = !!(cr & DS1374_REG_CR_WACE); in ds1374_read_alarm()
229 int cr; in ds1374_set_alarm() local
255 ret = cr = i2c_smbus_read_byte_data(client, DS1374_REG_CR); in ds1374_set_alarm()
261 cr &= ~DS1374_REG_CR_WACE; in ds1374_set_alarm()
263 ret = i2c_smbus_write_byte_data(client, DS1374_REG_CR, cr); in ds1374_set_alarm()
272 cr |= DS1374_REG_CR_WACE | DS1374_REG_CR_AIE; in ds1374_set_alarm()
273 cr &= ~DS1374_REG_CR_WDALM; in ds1374_set_alarm()
275 ret = i2c_smbus_write_byte_data(client, DS1374_REG_CR, cr); in ds1374_set_alarm()
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| D | rtc-stm32.c | 97 u16 cr; member
210 unsigned int status, cr; in stm32_rtc_alarm_irq() local
215 cr = readl_relaxed(rtc->base + regs->cr); in stm32_rtc_alarm_irq()
218 (cr & STM32_RTC_CR_ALRAIE)) { in stm32_rtc_alarm_irq()
342 unsigned int alrmar, cr, status; in stm32_rtc_read_alarm() local
345 cr = readl_relaxed(rtc->base + regs->cr); in stm32_rtc_read_alarm()
398 alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0; in stm32_rtc_read_alarm()
409 unsigned int cr; in stm32_rtc_alarm_irq_enable() local
411 cr = readl_relaxed(rtc->base + regs->cr); in stm32_rtc_alarm_irq_enable()
417 cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE); in stm32_rtc_alarm_irq_enable()
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| /drivers/tty/serial/ |
| D | fsl_linflexuart.c | 329 unsigned long cr, ier, cr1; in linflex_setup_watermark() local
336 cr = readl(sport->membase + UARTCR); in linflex_setup_watermark()
337 cr &= ~(LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN); in linflex_setup_watermark()
338 writel(cr, sport->membase + UARTCR); in linflex_setup_watermark()
364 cr = (LINFLEXD_UARTCR_RXEN | LINFLEXD_UARTCR_TXEN | in linflex_setup_watermark()
367 writel(cr, sport->membase + UARTCR); in linflex_setup_watermark()
419 unsigned long cr, old_cr, cr1; in linflex_set_termios() local
422 cr = readl(port->membase + UARTCR); in linflex_set_termios()
423 old_cr = cr; in linflex_set_termios()
454 cr = old_cr & ~LINFLEXD_UARTCR_WL1 & ~LINFLEXD_UARTCR_WL0; in linflex_set_termios()
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| D | apbuart.c | 43 unsigned int cr; in apbuart_stop_tx() local
45 cr = UART_GET_CTRL(port); in apbuart_stop_tx()
46 cr &= ~UART_CTRL_TI; in apbuart_stop_tx()
47 UART_PUT_CTRL(port, cr); in apbuart_stop_tx()
52 unsigned int cr; in apbuart_start_tx() local
54 cr = UART_GET_CTRL(port); in apbuart_start_tx()
55 cr |= UART_CTRL_TI; in apbuart_start_tx()
56 UART_PUT_CTRL(port, cr); in apbuart_start_tx()
64 unsigned int cr; in apbuart_stop_rx() local
66 cr = UART_GET_CTRL(port); in apbuart_stop_rx()
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| D | amba-pl010.c | 63 unsigned int cr; in pl010_stop_tx() local
65 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_tx()
66 cr &= ~UART010_CR_TIE; in pl010_stop_tx()
67 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_tx()
74 unsigned int cr; in pl010_start_tx() local
76 cr = readb(uap->port.membase + UART010_CR); in pl010_start_tx()
77 cr |= UART010_CR_TIE; in pl010_start_tx()
78 writel(cr, uap->port.membase + UART010_CR); in pl010_start_tx()
85 unsigned int cr; in pl010_stop_rx() local
87 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_rx()
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| /drivers/net/ethernet/xilinx/ |
| D | xilinx_axienet_main.c | 241 u32 cr; in axienet_dma_bd_init() local
300 cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET); in axienet_dma_bd_init()
302 cr = ((cr & ~XAXIDMA_COALESCE_MASK) | in axienet_dma_bd_init()
305 cr = ((cr & ~XAXIDMA_DELAY_MASK) | in axienet_dma_bd_init()
308 cr |= XAXIDMA_IRQ_ALL_MASK; in axienet_dma_bd_init()
310 axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET, cr); in axienet_dma_bd_init()
313 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_dma_bd_init()
315 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) | in axienet_dma_bd_init()
318 cr = (((cr & ~XAXIDMA_DELAY_MASK)) | in axienet_dma_bd_init()
321 cr |= XAXIDMA_IRQ_ALL_MASK; in axienet_dma_bd_init()
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| /drivers/scsi/ |
| D | BusLogic.h | 280 } cr; member
1120 union blogic_cntrl_reg cr; in blogic_busreset() local
1121 cr.all = 0; in blogic_busreset()
1122 cr.cr.bus_reset = true; in blogic_busreset()
1123 outb(cr.all, adapter->io_addr + BLOGIC_CNTRL_REG); in blogic_busreset()
1128 union blogic_cntrl_reg cr; in blogic_intreset() local
1129 cr.all = 0; in blogic_intreset()
1130 cr.cr.int_reset = true; in blogic_intreset()
1131 outb(cr.all, adapter->io_addr + BLOGIC_CNTRL_REG); in blogic_intreset()
1136 union blogic_cntrl_reg cr; in blogic_softreset() local
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| /drivers/iommu/ |
| D | omap-iommu-debug.c | 135 static ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr, in iotlb_dump_cr() argument
138 seq_printf(s, "%08x %08x %01x\n", cr->cam, cr->ram, in iotlb_dump_cr()
139 (cr->cam & MMU_CAM_P) ? 1 : 0); in iotlb_dump_cr()
146 struct cr_regs *cr; in omap_dump_tlb_entries() local
150 cr = kcalloc(num, sizeof(*cr), GFP_KERNEL); in omap_dump_tlb_entries()
151 if (!cr) in omap_dump_tlb_entries()
154 num = __dump_tlb_entries(obj, cr, num); in omap_dump_tlb_entries()
156 iotlb_dump_cr(obj, cr + i, s); in omap_dump_tlb_entries()
157 kfree(cr); in omap_dump_tlb_entries()
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| D | omap-iommu.c | 211 static u32 iotlb_cr_to_virt(struct cr_regs *cr) in iotlb_cr_to_virt() argument
213 u32 page_size = cr->cam & MMU_CAM_PGSZ_MASK; in iotlb_cr_to_virt()
214 u32 mask = get_cam_va_mask(cr->cam & page_size); in iotlb_cr_to_virt()
216 return cr->cam & mask; in iotlb_cr_to_virt()
270 static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) in iotlb_read_cr() argument
272 cr->cam = iommu_read_reg(obj, MMU_READ_CAM); in iotlb_read_cr()
273 cr->ram = iommu_read_reg(obj, MMU_READ_RAM); in iotlb_read_cr()
276 static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr) in iotlb_load_cr() argument
278 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); in iotlb_load_cr()
279 iommu_write_reg(obj, cr->ram, MMU_RAM); in iotlb_load_cr()
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| /drivers/spi/ |
| D | spi-sifive.c | 170 u32 cr; in sifive_spi_prep_transfer() local
174 cr = DIV_ROUND_UP(clk_get_rate(spi->clk) >> 1, t->speed_hz) - 1; in sifive_spi_prep_transfer()
175 cr &= SIFIVE_SPI_SCKDIV_DIV_MASK; in sifive_spi_prep_transfer()
176 sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, cr); in sifive_spi_prep_transfer()
181 cr = SIFIVE_SPI_FMT_LEN(t->bits_per_word); in sifive_spi_prep_transfer()
184 cr |= SIFIVE_SPI_FMT_PROTO_QUAD; in sifive_spi_prep_transfer()
187 cr |= SIFIVE_SPI_FMT_PROTO_DUAL; in sifive_spi_prep_transfer()
190 cr |= SIFIVE_SPI_FMT_PROTO_SINGLE; in sifive_spi_prep_transfer()
194 cr |= SIFIVE_SPI_FMT_ENDIAN; in sifive_spi_prep_transfer()
196 cr |= SIFIVE_SPI_FMT_DIR; in sifive_spi_prep_transfer()
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| D | spi-stm32-qspi.c | 132 u32 cr, sr; in stm32_qspi_irq() local
134 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
137 if (cr & CR_SMIE && sr & SR_SMF) { in stm32_qspi_irq()
139 cr &= ~CR_SMIE; in stm32_qspi_irq()
140 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
148 cr &= ~CR_TCIE & ~CR_TEIE; in stm32_qspi_irq()
149 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
221 u32 cr, t_out; in stm32_qspi_tx_dma() local
247 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
259 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
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| D | spi-xilinx.c | 189 u16 cr; in xilinx_spi_chipselect() local
199 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK; in xilinx_spi_chipselect()
201 cr |= XSPI_CR_CPHA; in xilinx_spi_chipselect()
203 cr |= XSPI_CR_CPOL; in xilinx_spi_chipselect()
205 cr |= XSPI_CR_LSB_FIRST; in xilinx_spi_chipselect()
207 cr |= XSPI_CR_LOOP; in xilinx_spi_chipselect()
208 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); in xilinx_spi_chipselect()
243 u16 cr = 0; in xilinx_spi_txrx_bufs() local
255 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); in xilinx_spi_txrx_bufs()
256 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, in xilinx_spi_txrx_bufs()
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| D | spi-hisi-kunpeng.c | 115 u32 cr; member
316 u32 cr = FIELD_PREP(CR_SPD_MODE_MASK, 1); in hisi_spi_prepare_cr() local
318 cr |= FIELD_PREP(CR_CPHA_MASK, (spi->mode & SPI_CPHA) ? 1 : 0); in hisi_spi_prepare_cr()
319 cr |= FIELD_PREP(CR_CPOL_MASK, (spi->mode & SPI_CPOL) ? 1 : 0); in hisi_spi_prepare_cr()
320 cr |= FIELD_PREP(CR_LOOP_MASK, (spi->mode & SPI_LOOP) ? 1 : 0); in hisi_spi_prepare_cr()
322 return cr; in hisi_spi_prepare_cr()
381 u32 cr = chip->cr; in hisi_spi_transfer_one() local
386 cr |= FIELD_PREP(CR_DIV_PRE_MASK, chip->div_pre); in hisi_spi_transfer_one()
387 cr |= FIELD_PREP(CR_DIV_POST_MASK, chip->div_post); in hisi_spi_transfer_one()
388 cr |= FIELD_PREP(CR_BPW_MASK, transfer->bits_per_word - 1); in hisi_spi_transfer_one()
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| /drivers/crypto/allwinner/sun4i-ss/ |
| D | sun4i-ss-core.c | 360 unsigned long cr; in sun4i_ss_probe() local
421 cr = clk_get_rate(ss->busclk); in sun4i_ss_probe()
422 if (cr >= cr_ahb) in sun4i_ss_probe()
424 cr, cr / 1000000, cr_ahb); in sun4i_ss_probe()
427 cr, cr / 1000000, cr_ahb); in sun4i_ss_probe()
429 cr = clk_get_rate(ss->ssclk); in sun4i_ss_probe()
430 if (cr <= cr_mod) in sun4i_ss_probe()
431 if (cr < cr_mod) in sun4i_ss_probe()
433 cr, cr / 1000000, cr_mod); in sun4i_ss_probe()
436 cr, cr / 1000000, cr_mod); in sun4i_ss_probe()
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| /drivers/pwm/ |
| D | pwm-imx27.c | 180 u32 cr; in pwm_imx27_sw_reset() local
185 cr = readl(imx->mmio_base + MX3_PWMCR); in pwm_imx27_sw_reset()
186 } while ((cr & MX3_PWMCR_SWR) && in pwm_imx27_sw_reset()
189 if (cr & MX3_PWMCR_SWR) in pwm_imx27_sw_reset()
224 u32 cr; in pwm_imx27_apply() local
274 cr = MX3_PWMCR_PRESCALER_SET(prescale) | in pwm_imx27_apply()
280 cr |= FIELD_PREP(MX3_PWMCR_POUTC, in pwm_imx27_apply()
284 cr |= MX3_PWMCR_EN; in pwm_imx27_apply()
286 writel(cr, imx->mmio_base + MX3_PWMCR); in pwm_imx27_apply()
|