| /drivers/net/ethernet/huawei/hinic/ |
| D | hinic_hw_csr.h | 21 #define HINIC_CSR_DMA_ATTR_ADDR(idx) \ argument
22 (HINIC_DMA_ATTR_BASE + (idx) * HINIC_DMA_ATTR_STRIDE)
27 #define HINIC_CSR_PPF_ELECTION_ADDR(idx) \ argument
28 (HINIC_ELECTION_BASE + (idx) * HINIC_PPF_ELECTION_STRIDE)
35 #define HINIC_CSR_API_CMD_CHAIN_HEAD_HI_ADDR(idx) \ argument
36 (HINIC_CSR_API_CMD_BASE + 0x0 + (idx) * HINIC_CSR_API_CMD_STRIDE)
38 #define HINIC_CSR_API_CMD_CHAIN_HEAD_LO_ADDR(idx) \ argument
39 (HINIC_CSR_API_CMD_BASE + 0x4 + (idx) * HINIC_CSR_API_CMD_STRIDE)
41 #define HINIC_CSR_API_CMD_STATUS_HI_ADDR(idx) \ argument
42 (HINIC_CSR_API_CMD_BASE + 0x8 + (idx) * HINIC_CSR_API_CMD_STRIDE)
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| /drivers/crypto/ccree/ |
| D | cc_aead.c | 303 unsigned int idx = 0; in hmac_setkey() local
309 hw_desc_init(&desc[idx]); in hmac_setkey()
310 set_cipher_mode(&desc[idx], hash_mode); in hmac_setkey()
311 set_din_sram(&desc[idx], in hmac_setkey()
315 set_flow_mode(&desc[idx], S_DIN_to_HASH); in hmac_setkey()
316 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); in hmac_setkey()
317 idx++; in hmac_setkey()
320 hw_desc_init(&desc[idx]); in hmac_setkey()
321 set_cipher_mode(&desc[idx], hash_mode); in hmac_setkey()
322 set_din_const(&desc[idx], 0, ctx->hash_len); in hmac_setkey()
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| D | cc_hash.c | 342 int idx) in cc_fin_result() argument
350 hw_desc_init(&desc[idx]); in cc_fin_result()
351 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode); in cc_fin_result()
352 set_dout_dlli(&desc[idx], state->digest_result_dma_addr, digestsize, in cc_fin_result()
354 set_queue_last_ind(ctx->drvdata, &desc[idx]); in cc_fin_result()
355 set_flow_mode(&desc[idx], S_HASH_to_DOUT); in cc_fin_result()
356 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); in cc_fin_result()
357 set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); in cc_fin_result()
358 cc_set_endianity(ctx->hash_mode, &desc[idx]); in cc_fin_result()
359 idx++; in cc_fin_result()
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| /drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_calendar.c | 162 u32 cal[7], value, idx, portno; in sparx5_config_auto_calendar() local
216 for (idx = 0; idx < ARRAY_SIZE(cal); idx++) in sparx5_config_auto_calendar()
217 spx5_wr(cal[idx], sparx5, QSYS_CAL_AUTO(idx)); in sparx5_config_auto_calendar()
228 for (idx = 2; idx < 5; idx++) in sparx5_config_auto_calendar()
231 HSCH_OUTB_SHARE_ENA(idx)); in sparx5_config_auto_calendar()
256 u32 idx = 0, len = 0; in sparx5_dsm_cal_len() local
258 while (idx < SPX5_DSM_CAL_LEN) { in sparx5_dsm_cal_len()
259 if (cal[idx] != SPX5_DSM_CAL_EMPTY) in sparx5_dsm_cal_len()
261 idx++; in sparx5_dsm_cal_len()
268 u32 idx = 0, tmp; in sparx5_dsm_cp_cal() local
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| D | sparx5_main.c | 218 int idx, jdx; in sparx5_create_targets() local
220 for (idx = 0, jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { in sparx5_create_targets()
223 if (idx == iomap->range) { in sparx5_create_targets()
224 range_id[idx] = jdx; in sparx5_create_targets()
225 idx++; in sparx5_create_targets()
228 for (idx = 0; idx < IO_RANGES; idx++) { in sparx5_create_targets()
229 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, in sparx5_create_targets()
230 idx); in sparx5_create_targets()
231 if (!iores[idx]) { in sparx5_create_targets()
235 iomem[idx] = devm_ioremap(sparx5->dev, in sparx5_create_targets()
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| /drivers/net/can/sja1000/ |
| D | sja1000_isa.c | 122 int idx = pdev->id; in sja1000_isa_probe() local
126 idx, port[idx], mem[idx], irq[idx]); in sja1000_isa_probe()
128 if (mem[idx]) { in sja1000_isa_probe()
129 if (!request_mem_region(mem[idx], iosize, DRV_NAME)) { in sja1000_isa_probe()
133 base = ioremap(mem[idx], iosize); in sja1000_isa_probe()
139 if (indirect[idx] > 0 || in sja1000_isa_probe()
140 (indirect[idx] == -1 && indirect[0] > 0)) in sja1000_isa_probe()
142 if (!request_region(port[idx], iosize, DRV_NAME)) { in sja1000_isa_probe()
155 dev->irq = irq[idx]; in sja1000_isa_probe()
157 if (mem[idx]) { in sja1000_isa_probe()
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| /drivers/net/can/cc770/ |
| D | cc770_isa.c | 167 int idx = pdev->id; in cc770_isa_probe() local
172 idx, port[idx], mem[idx], irq[idx]); in cc770_isa_probe()
173 if (mem[idx]) { in cc770_isa_probe()
174 if (!request_mem_region(mem[idx], iosize, KBUILD_MODNAME)) { in cc770_isa_probe()
178 base = ioremap(mem[idx], iosize); in cc770_isa_probe()
184 if (indirect[idx] > 0 || in cc770_isa_probe()
185 (indirect[idx] == -1 && indirect[0] > 0)) in cc770_isa_probe()
187 if (!request_region(port[idx], iosize, KBUILD_MODNAME)) { in cc770_isa_probe()
200 dev->irq = irq[idx]; in cc770_isa_probe()
202 if (mem[idx]) { in cc770_isa_probe()
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| /drivers/clk/uniphier/ |
| D | clk-uniphier-sys.c | 23 #define UNIPHIER_LD4_SYS_CLK_NAND(idx) \ argument
25 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
27 #define UNIPHIER_PRO5_SYS_CLK_NAND(idx) \ argument
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
31 #define UNIPHIER_LD11_SYS_CLK_NAND(idx) \ argument
33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
35 #define UNIPHIER_SYS_CLK_NAND_4X(idx) \ argument
36 UNIPHIER_CLK_FACTOR("nand-4x", (idx), "nand", 4, 1)
38 #define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \ argument
39 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
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| /drivers/gpu/drm/radeon/ |
| D | evergreen_cs.c | 755 unsigned idx) in evergreen_cs_track_validate_texture() argument
763 texdw[0] = radeon_get_ib_value(p, idx + 0); in evergreen_cs_track_validate_texture()
764 texdw[1] = radeon_get_ib_value(p, idx + 1); in evergreen_cs_track_validate_texture()
765 texdw[2] = radeon_get_ib_value(p, idx + 2); in evergreen_cs_track_validate_texture()
766 texdw[3] = radeon_get_ib_value(p, idx + 3); in evergreen_cs_track_validate_texture()
767 texdw[4] = radeon_get_ib_value(p, idx + 4); in evergreen_cs_track_validate_texture()
768 texdw[5] = radeon_get_ib_value(p, idx + 5); in evergreen_cs_track_validate_texture()
769 texdw[6] = radeon_get_ib_value(p, idx + 6); in evergreen_cs_track_validate_texture()
770 texdw[7] = radeon_get_ib_value(p, idx + 7); in evergreen_cs_track_validate_texture()
1049 unsigned idx, unsigned reg) in evergreen_packet0_check() argument
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| D | r600_cs.c | 839 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx); in r600_cs_common_vline_parse()
850 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); in r600_cs_common_vline_parse()
866 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { in r600_cs_common_vline_parse()
871 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { in r600_cs_common_vline_parse()
877 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); in r600_cs_common_vline_parse()
881 h_idx = p->idx - 2; in r600_cs_common_vline_parse()
882 p->idx += wait_reg_mem.count + 2; in r600_cs_common_vline_parse()
883 p->idx += p3reloc.count + 2; in r600_cs_common_vline_parse()
920 unsigned idx, unsigned reg) in r600_packet0_check() argument
929 idx, reg); in r600_packet0_check()
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| /drivers/net/ethernet/ti/ |
| D | cpsw_ale.c | 107 int idx, idx2; in cpsw_ale_get_field() local
110 idx = start / 32; in cpsw_ale_get_field()
113 if (idx != idx2) { in cpsw_ale_get_field()
117 start -= idx * 32; in cpsw_ale_get_field()
118 idx = 2 - idx; /* flip */ in cpsw_ale_get_field()
119 return (hi_val + (ale_entry[idx] >> start)) & BITMASK(bits); in cpsw_ale_get_field()
125 int idx, idx2; in cpsw_ale_set_field() local
128 idx = start / 32; in cpsw_ale_set_field()
131 if (idx != idx2) { in cpsw_ale_set_field()
136 start -= idx * 32; in cpsw_ale_set_field()
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hw_sspp.c | 138 u32 *idx) in _sspp_subblk_offset() argument
150 *idx = sblk->src_blk.base; in _sspp_subblk_offset()
155 *idx = sblk->scaler_blk.base; in _sspp_subblk_offset()
159 *idx = sblk->csc_blk.base; in _sspp_subblk_offset()
173 u32 idx; in dpu_hw_sspp_setup_multirect() local
175 if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) in dpu_hw_sspp_setup_multirect()
186 mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx); in dpu_hw_sspp_setup_multirect()
194 DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask); in dpu_hw_sspp_setup_multirect()
200 u32 idx; in _sspp_setup_opmode() local
204 _sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED2, &idx) || in _sspp_setup_opmode()
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| /drivers/net/ethernet/chelsio/cxgb/ |
| D | fpga_defs.h | 215 #define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg)) argument
217 #define MAC_REG_IDLO(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_LO) argument
218 #define MAC_REG_IDHI(idx) MAC_REG_ADDR(idx, A_GMAC_MACID_HI) argument
219 #define MAC_REG_CSR(idx) MAC_REG_ADDR(idx, A_GMAC_CSR) argument
220 #define MAC_REG_IFS(idx) MAC_REG_ADDR(idx, A_GMAC_IFS) argument
221 #define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN) argument
222 #define MAC_REG_LINKDLY(idx) MAC_REG_ADDR(idx, A_GMAC_LNK_DLY) argument
223 #define MAC_REG_PAUSETIME(idx) MAC_REG_ADDR(idx, A_GMAC_PAUSETIME) argument
224 #define MAC_REG_CASTLO(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_LO) argument
225 #define MAC_REG_MCASTHI(idx) MAC_REG_ADDR(idx, A_GMAC_MCAST_HI) argument
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| /drivers/net/wireless/mediatek/mt7601u/ |
| D | main.c | 49 unsigned int idx = 0; in mt7601u_add_interface() local
50 unsigned int wcid = GROUP_WCID(idx); in mt7601u_add_interface()
57 mvif->idx = idx; in mt7601u_add_interface()
65 mvif->group_wcid.idx = wcid; in mt7601u_add_interface()
76 unsigned int wcid = mvif->group_wcid.idx; in mt7601u_remove_interface()
189 int i, idx = 0; in mt76_wcid_alloc() local
192 idx = ffs(~dev->wcid_mask[i]); in mt76_wcid_alloc()
193 if (!idx) in mt76_wcid_alloc()
196 idx--; in mt76_wcid_alloc()
197 dev->wcid_mask[i] |= BIT(idx); in mt76_wcid_alloc()
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| /drivers/input/misc/ |
| D | ad714x.c | 213 static void ad714x_button_state_machine(struct ad714x_chip *ad714x, int idx) in ad714x_button_state_machine() argument
215 struct ad714x_button_plat *hw = &ad714x->hw->button[idx]; in ad714x_button_state_machine()
216 struct ad714x_button_drv *sw = &ad714x->sw->button[idx]; in ad714x_button_state_machine()
222 dev_dbg(ad714x->dev, "button %d touched\n", idx); in ad714x_button_state_machine()
232 dev_dbg(ad714x->dev, "button %d released\n", idx); in ad714x_button_state_machine()
248 static void ad714x_slider_cal_sensor_val(struct ad714x_chip *ad714x, int idx) in ad714x_slider_cal_sensor_val() argument
250 struct ad714x_slider_plat *hw = &ad714x->hw->slider[idx]; in ad714x_slider_cal_sensor_val()
266 static void ad714x_slider_cal_highest_stage(struct ad714x_chip *ad714x, int idx) in ad714x_slider_cal_highest_stage() argument
268 struct ad714x_slider_plat *hw = &ad714x->hw->slider[idx]; in ad714x_slider_cal_highest_stage()
269 struct ad714x_slider_drv *sw = &ad714x->sw->slider[idx]; in ad714x_slider_cal_highest_stage()
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| /drivers/media/usb/pvrusb2/ |
| D | pvrusb2-encoder.c | 30 unsigned int idx,addr; in pvr2_encoder_write_words() local
51 for (idx = 0; idx < chunkCnt; idx++) { in pvr2_encoder_write_words()
52 addr = idx + offs; in pvr2_encoder_write_words()
56 PVR2_DECOMPOSE_LE(hdw->cmd_buffer, bAddr,data[idx]); in pvr2_encoder_write_words()
76 unsigned int idx; in pvr2_encoder_read_words() local
110 for (idx = 0; idx < chunkCnt; idx++) { in pvr2_encoder_read_words()
111 data[idx] = PVR2_COMPOSE_LE(hdw->cmd_buffer,idx*4); in pvr2_encoder_read_words()
137 unsigned int idx; in pvr2_encoder_cmd() local
205 for (idx = 0; idx < arg_cnt_send; idx++) { in pvr2_encoder_cmd()
206 wrData[idx+4] = argp[idx]; in pvr2_encoder_cmd()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gk104.c | 145 read_clk(struct gk104_clk *clk, int idx) in read_clk() argument
148 u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4)); in read_clk()
151 if (idx < 7) { in read_clk()
153 if (ssel & (1 << idx)) { in read_clk()
154 sclk = read_pll(clk, 0x137000 + (idx * 0x20)); in read_clk()
157 sclk = read_div(clk, idx, 0x137160, 0x1371d0); in read_clk()
161 u32 ssrc = nvkm_rd32(device, 0x137160 + (idx * 0x04)); in read_clk()
163 sclk = read_div(clk, idx, 0x137160, 0x1371d0); in read_clk()
172 sclk = read_div(clk, idx, 0x137160, 0x1371d0); in read_clk()
223 calc_div(struct gk104_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv) in calc_div() argument
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| D | gf100.c | 133 read_clk(struct gf100_clk *clk, int idx) in read_clk() argument
136 u32 sctl = nvkm_rd32(device, 0x137250 + (idx * 4)); in read_clk()
140 if (ssel & (1 << idx)) { in read_clk()
141 if (idx < 7) in read_clk()
142 sclk = read_pll(clk, 0x137000 + (idx * 0x20)); in read_clk()
147 sclk = read_div(clk, idx, 0x137160, 0x1371d0); in read_clk()
210 calc_div(struct gf100_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv) in calc_div() argument
221 calc_src(struct gf100_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv) in calc_src() argument
243 sclk = read_vco(clk, 0x137160 + (idx * 4)); in calc_src()
244 if (idx < 7) in calc_src()
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| /drivers/media/dvb-core/ |
| D | dvb_ringbuffer.c | 252 ssize_t dvb_ringbuffer_pkt_read_user(struct dvb_ringbuffer *rbuf, size_t idx, in dvb_ringbuffer_pkt_read_user() argument
259 pktlen = rbuf->data[idx] << 8; in dvb_ringbuffer_pkt_read_user()
260 pktlen |= rbuf->data[(idx + 1) % rbuf->size]; in dvb_ringbuffer_pkt_read_user()
264 idx = (idx + DVB_RINGBUFFER_PKTHDRSIZE + offset) % rbuf->size; in dvb_ringbuffer_pkt_read_user()
266 split = ((idx + len) > rbuf->size) ? rbuf->size - idx : 0; in dvb_ringbuffer_pkt_read_user()
268 if (copy_to_user(buf, rbuf->data+idx, split)) in dvb_ringbuffer_pkt_read_user()
272 idx = 0; in dvb_ringbuffer_pkt_read_user()
274 if (copy_to_user(buf, rbuf->data+idx, todo)) in dvb_ringbuffer_pkt_read_user()
280 ssize_t dvb_ringbuffer_pkt_read(struct dvb_ringbuffer *rbuf, size_t idx, in dvb_ringbuffer_pkt_read() argument
287 pktlen = rbuf->data[idx] << 8; in dvb_ringbuffer_pkt_read()
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| /drivers/perf/ |
| D | arm_smmuv3_pmu.c | 145 struct perf_event *event, int idx);
150 unsigned int idx; in smmu_pmu_enable_quirk_hip08_09() local
152 for_each_set_bit(idx, smmu_pmu->used_counters, smmu_pmu->num_counters) in smmu_pmu_enable_quirk_hip08_09()
153 smmu_pmu_apply_event_filter(smmu_pmu, smmu_pmu->events[idx], idx); in smmu_pmu_enable_quirk_hip08_09()
169 unsigned int idx; in smmu_pmu_disable_quirk_hip08_09() local
176 for_each_set_bit(idx, smmu_pmu->used_counters, smmu_pmu->num_counters) in smmu_pmu_disable_quirk_hip08_09()
177 writel(0xffff, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx)); in smmu_pmu_disable_quirk_hip08_09()
183 u32 idx, u64 value) in smmu_pmu_counter_set_value() argument
186 writeq(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 8)); in smmu_pmu_counter_set_value()
188 writel(value, smmu_pmu->reloc_base + SMMU_PMCG_EVCNTR(idx, 4)); in smmu_pmu_counter_set_value()
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| D | qcom_l2_pmu.c | 155 static inline u32 idx_to_reg_bit(u32 idx) in idx_to_reg_bit() argument
157 if (idx == l2_cycle_ctr_idx) in idx_to_reg_bit()
160 return BIT(idx); in idx_to_reg_bit()
188 static inline void cluster_pmu_counter_set_value(u32 idx, u64 value) in cluster_pmu_counter_set_value() argument
190 if (idx == l2_cycle_ctr_idx) in cluster_pmu_counter_set_value()
193 kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx), value); in cluster_pmu_counter_set_value()
196 static inline u64 cluster_pmu_counter_get_value(u32 idx) in cluster_pmu_counter_get_value() argument
200 if (idx == l2_cycle_ctr_idx) in cluster_pmu_counter_get_value()
203 value = kryo_l2_get_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx)); in cluster_pmu_counter_get_value()
208 static inline void cluster_pmu_counter_enable(u32 idx) in cluster_pmu_counter_enable() argument
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| D | qcom_l3_pmu.c | 196 int idx = event->hw.idx; in qcom_l3_cache__64bit_counter_start() local
202 gang |= GANG_EN(idx + 1); in qcom_l3_cache__64bit_counter_start()
207 writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1)); in qcom_l3_cache__64bit_counter_start()
208 writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx)); in qcom_l3_cache__64bit_counter_start()
214 writel_relaxed(EVSEL(0), l3pmu->regs + L3_HML3_PM_EVTYPE(idx + 1)); in qcom_l3_cache__64bit_counter_start()
215 writel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx)); in qcom_l3_cache__64bit_counter_start()
218 writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx + 1)); in qcom_l3_cache__64bit_counter_start()
219 writel_relaxed(PMCNTENSET(idx + 1), l3pmu->regs + L3_M_BC_CNTENSET); in qcom_l3_cache__64bit_counter_start()
220 writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx)); in qcom_l3_cache__64bit_counter_start()
221 writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET); in qcom_l3_cache__64bit_counter_start()
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| /drivers/irqchip/ |
| D | irq-bcm7120-l2.c | 60 unsigned int idx; in bcm7120_l2_intc_irq_handle() local
64 for (idx = 0; idx < b->n_words; idx++) { in bcm7120_l2_intc_irq_handle()
65 int base = idx * IRQS_PER_WORD; in bcm7120_l2_intc_irq_handle()
72 pending = irq_reg_readl(gc, b->stat_offset[idx]) & in bcm7120_l2_intc_irq_handle()
74 data->irq_map_mask[idx]; in bcm7120_l2_intc_irq_handle()
112 unsigned int idx; in bcm7120_l2_intc_init_one() local
129 for (idx = 0; idx < data->n_words; idx++) { in bcm7120_l2_intc_init_one()
131 l1_data->irq_map_mask[idx] |= in bcm7120_l2_intc_init_one()
133 irq * data->n_words + idx); in bcm7120_l2_intc_init_one()
135 l1_data->irq_map_mask[idx] = 0xffffffff; in bcm7120_l2_intc_init_one()
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| /drivers/media/pci/pt3/ |
| D | pt3_dma.c | 16 static u32 get_dma_base(int idx) in get_dma_base() argument
20 i = (idx == 1 || idx == 2) ? 3 - idx : idx; in get_dma_base()
61 static u8 *next_unit(struct pt3_adapter *adap, int *idx, int *ofs) in next_unit() argument
66 (*idx)++; in next_unit()
67 if (*idx == adap->num_bufs) in next_unit()
68 *idx = 0; in next_unit()
70 return &adap->buffer[*idx].data[*ofs]; in next_unit()
75 int idx, ofs; in pt3_proc_dma() local
77 idx = adap->buf_idx; in pt3_proc_dma()
80 if (adap->buffer[idx].data[ofs] == PT3_BUF_CANARY) in pt3_proc_dma()
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| /drivers/hwtracing/coresight/ |
| D | coresight-etm4x-cfg.c | 49 int err = -EINVAL, idx; in etm4_cfg_map_reg_offset() local
78 idx = (offset & GENMASK(3, 0)) / 4; in etm4_cfg_map_reg_offset()
79 if (idx < ETM_MAX_SEQ_STATES) { in etm4_cfg_map_reg_offset()
80 reg_csdev->driver_regval = &drvcfg->seq_ctrl[idx]; in etm4_cfg_map_reg_offset()
85 idx = (offset & GENMASK(4, 0)) / 4; in etm4_cfg_map_reg_offset()
88 CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask); in etm4_cfg_map_reg_offset()
89 CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask); in etm4_cfg_map_reg_offset()
90 CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask); in etm4_cfg_map_reg_offset()
94 idx = (offset & GENMASK(5, 0)) / 8; in etm4_cfg_map_reg_offset()
97 CHECKREGIDX(TRCCIDCVRn(0), ctxid_pid, idx, off_mask); in etm4_cfg_map_reg_offset()
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