| /drivers/gpio/ |
| D | gpio-omap.c | 77 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
83 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
108 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
111 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
117 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
120 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
124 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
125 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
127 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
128 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg()
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| D | gpio-rockchip.c | 76 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
79 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
81 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
87 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument
90 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
93 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_readl()
101 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_writel_bit() argument
105 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
108 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_writel_bit()
123 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_readl_bit() argument
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| D | gpio-brcmstb.c | 26 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
27 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
28 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
29 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
30 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
31 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
32 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
33 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
34 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
66 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local
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| D | gpio-i8255.c | 28 const unsigned long bank = io_port / 3; in i8255_get_port() local
31 return ioread8(&ppi[bank].port[ppi_port]) & mask; in i8255_get_port()
61 const unsigned long bank = io_port / 3; in i8255_set_port() local
66 spin_lock_irqsave(&state[bank].lock, flags); in i8255_set_port()
68 out_state = ioread8(&ppi[bank].port[ppi_port]); in i8255_set_port()
70 iowrite8(out_state, &ppi[bank].port[ppi_port]); in i8255_set_port()
72 spin_unlock_irqrestore(&state[bank].lock, flags); in i8255_set_port()
90 const unsigned long bank = io_port / 3; in i8255_direction_input() local
93 spin_lock_irqsave(&state[bank].lock, flags); in i8255_direction_input()
95 state[bank].control_state |= I8255_CONTROL_MODE_SET; in i8255_direction_input()
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| D | gpio-aspeed-sgpio.c | 104 const struct aspeed_sgpio_bank *bank, in bank_reg() argument
109 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
111 return gpio->base + bank->rdata_reg; in bank_reg()
113 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
115 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
117 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
119 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
121 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
123 return gpio->base + bank->tolerance_regs; in bank_reg()
136 unsigned int bank; in to_bank() local
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| D | gpio-f7188x.c | 95 struct f7188x_gpio_bank *bank; member
291 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); in f7188x_gpio_get_direction() local
292 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_get_direction()
300 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase)); in f7188x_gpio_get_direction()
316 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); in f7188x_gpio_direction_in() local
317 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_direction_in()
325 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase)); in f7188x_gpio_direction_in()
331 superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir); in f7188x_gpio_direction_in()
341 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip); in f7188x_gpio_get() local
342 struct f7188x_sio *sio = bank->data->sio; in f7188x_gpio_get()
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| /drivers/pinctrl/renesas/ |
| D | sh_pfc.h | 445 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
446 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
447 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
449 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ argument
450 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
451 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
452 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) argument
454 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
455 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
456 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
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| /drivers/pinctrl/samsung/ |
| D | pinctrl-exynos.c | 54 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
55 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
59 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
61 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
63 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
65 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
72 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_ack() local
73 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; in exynos_irq_ack()
75 writel(1 << irqd->hwirq, bank->eint_base + reg_pend); in exynos_irq_ack()
82 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_unmask() local
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| D | pinctrl-samsung.c | 358 struct samsung_pin_bank **bank) in pin_to_reg_bank() argument
370 if (bank) in pin_to_reg_bank()
371 *bank = b; in pin_to_reg_bank()
380 struct samsung_pin_bank *bank; in samsung_pinmux_setup() local
392 ®, &pin_offset, &bank); in samsung_pinmux_setup()
393 type = bank->type; in samsung_pinmux_setup()
402 raw_spin_lock_irqsave(&bank->slock, flags); in samsung_pinmux_setup()
409 raw_spin_unlock_irqrestore(&bank->slock, flags); in samsung_pinmux_setup()
435 struct samsung_pin_bank *bank; in samsung_pinconf_rw() local
444 &pin_offset, &bank); in samsung_pinconf_rw()
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| D | pinctrl-s3c24xx.c | 101 struct samsung_pin_bank *bank; member
134 struct samsung_pin_bank *bank, int pin) in s3c24xx_eint_set_function() argument
136 const struct samsung_pin_bank_type *bank_type = bank->type; in s3c24xx_eint_set_function()
144 reg = d->virt_base + bank->pctl_offset; in s3c24xx_eint_set_function()
148 raw_spin_lock_irqsave(&bank->slock, flags); in s3c24xx_eint_set_function()
152 val |= bank->eint_func << shift; in s3c24xx_eint_set_function()
155 raw_spin_unlock_irqrestore(&bank->slock, flags); in s3c24xx_eint_set_function()
160 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data); in s3c24xx_eint_type() local
161 struct samsung_pinctrl_drv_data *d = bank->drvdata; in s3c24xx_eint_type()
162 int index = bank->eint_offset + data->hwirq; in s3c24xx_eint_type()
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| D | pinctrl-s3c64xx.c | 213 struct samsung_pin_bank *bank; member
268 struct samsung_pin_bank *bank, int pin) in s3c64xx_irq_set_function() argument
270 const struct samsung_pin_bank_type *bank_type = bank->type; in s3c64xx_irq_set_function()
278 reg = d->virt_base + bank->pctl_offset; in s3c64xx_irq_set_function()
289 raw_spin_lock_irqsave(&bank->slock, flags); in s3c64xx_irq_set_function()
293 val |= bank->eint_func << shift; in s3c64xx_irq_set_function()
296 raw_spin_unlock_irqrestore(&bank->slock, flags); in s3c64xx_irq_set_function()
305 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in s3c64xx_gpio_irq_set_mask() local
306 struct samsung_pinctrl_drv_data *d = bank->drvdata; in s3c64xx_gpio_irq_set_mask()
307 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; in s3c64xx_gpio_irq_set_mask()
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| /drivers/crypto/qat/qat_common/ |
| D | adf_transport.c | 40 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
42 spin_lock(&bank->lock); in adf_reserve_ring()
43 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
44 spin_unlock(&bank->lock); in adf_reserve_ring()
47 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
48 spin_unlock(&bank->lock); in adf_reserve_ring()
52 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_unreserve_ring() argument
54 spin_lock(&bank->lock); in adf_unreserve_ring()
55 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
56 spin_unlock(&bank->lock); in adf_unreserve_ring()
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| D | adf_gen4_hw_data.h | 28 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
30 ADF_RING_BUNDLE_SIZE * (bank) + \
32 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
34 ADF_RING_BUNDLE_SIZE * (bank) + \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
38 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
41 ADF_RING_BUNDLE_SIZE * (bank) + \
43 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
46 u32 _bank = bank; \
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| D | adf_transport_debug.c | 44 struct adf_etr_bank_data *bank = ring->bank; in adf_ring_show() local
45 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev); in adf_ring_show()
46 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show()
51 head = csr_ops->read_csr_ring_head(csr, bank->bank_number, in adf_ring_show()
53 tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number, in adf_ring_show()
55 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
61 ring->ring_number, ring->bank->bank_number); in adf_ring_show()
104 ring->bank->bank_debug_dir, in adf_ring_debugfs_add()
121 struct adf_etr_bank_data *bank = sfile->private; in adf_bank_start() local
122 u8 num_rings_per_bank = GET_NUM_RINGS_PER_BANK(bank->accel_dev); in adf_bank_start()
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| D | adf_gen2_hw_data.h | 31 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
32 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
34 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
35 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
37 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
38 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
40 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
41 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
43 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
48 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
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| D | adf_gen4_hw_data.c | 13 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
15 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
18 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
21 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
24 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
26 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
29 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
32 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
35 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument
37 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
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| D | adf_gen2_hw_data.c | 119 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
121 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
124 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
127 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
130 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
132 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
135 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
138 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
141 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument
143 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
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| /drivers/pinctrl/stm32/ |
| D | pinctrl-stm32.c | 156 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
159 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
160 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
163 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
166 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
168 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
169 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
172 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
175 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
176 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
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| /drivers/net/phy/mscc/ |
| D | mscc_macsec.c | 23 enum macsec_bank bank, u32 reg) in vsc8584_macsec_phy_read() argument
34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_read()
36 if (bank >> 2 == 0x1) in vsc8584_macsec_phy_read()
38 bank &= 0x3; in vsc8584_macsec_phy_read()
40 bank = 0; in vsc8584_macsec_phy_read()
45 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_read()
62 enum macsec_bank bank, u32 reg, u32 val) in vsc8584_macsec_phy_write() argument
72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_write()
74 if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) in vsc8584_macsec_phy_write()
75 bank &= 0x3; in vsc8584_macsec_phy_write()
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| /drivers/bus/ |
| D | uniphier-system-bus.c | 35 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member
39 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument
45 bank, addr, paddr, size); in uniphier_system_bus_add_bank()
47 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank()
48 dev_err(priv->dev, "unsupported bank number %d\n", bank); in uniphier_system_bus_add_bank()
52 if (priv->bank[bank].base || priv->bank[bank].end) { in uniphier_system_bus_add_bank()
54 "range for bank %d has already been specified\n", bank); in uniphier_system_bus_add_bank()
86 priv->bank[bank].base = paddr; in uniphier_system_bus_add_bank()
87 priv->bank[bank].end = end; in uniphier_system_bus_add_bank()
90 bank, priv->bank[bank].base, priv->bank[bank].end); in uniphier_system_bus_add_bank()
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| /drivers/dma/ipu/ |
| D | ipu_irq.c | 72 struct ipu_irq_bank *bank; member
96 struct ipu_irq_bank *bank; in ipu_irq_unmask() local
102 bank = map->bank; in ipu_irq_unmask()
103 if (!bank) { in ipu_irq_unmask()
109 reg = ipu_read_reg(bank->ipu, bank->control); in ipu_irq_unmask()
111 ipu_write_reg(bank->ipu, reg, bank->control); in ipu_irq_unmask()
119 struct ipu_irq_bank *bank; in ipu_irq_mask() local
125 bank = map->bank; in ipu_irq_mask()
126 if (!bank) { in ipu_irq_mask()
132 reg = ipu_read_reg(bank->ipu, bank->control); in ipu_irq_mask()
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| /drivers/pinctrl/ |
| D | pinctrl-rockchip.c | 658 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
661 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
668 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
1018 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
1021 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1028 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1043 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
1045 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
1056 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1061 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
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| D | pinctrl-oxnas.c | 30 #define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK) argument
71 unsigned int bank; member
275 .bank = _pin / PINS_PER_BANK, \
601 fname, pg->bank, pg->pin, in oxnas_ox810se_pinmux_enable()
605 (pg->bank ? in oxnas_ox810se_pinmux_enable()
612 (pg->bank ? in oxnas_ox810se_pinmux_enable()
619 (pg->bank ? in oxnas_ox810se_pinmux_enable()
645 unsigned int offset = (pg->bank ? PINMUX_820_BANK_OFFSET : 0); in oxnas_ox820_pinmux_enable()
652 fname, pg->bank, pg->pin, in oxnas_ox820_pinmux_enable()
697 struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc); in oxnas_ox810se_gpio_request_enable() local
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| D | pinctrl-microchip-sgpio.c | 355 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_pinconf_get() local
357 struct sgpio_priv *priv = bank->priv; in sgpio_pinconf_get()
365 val = bank->is_input; in sgpio_pinconf_get()
369 val = !bank->is_input; in sgpio_pinconf_get()
373 if (bank->is_input) in sgpio_pinconf_get()
390 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_pinconf_set() local
391 struct sgpio_priv *priv = bank->priv; in sgpio_pinconf_set()
404 if (bank->is_input) in sgpio_pinconf_set()
456 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); in sgpio_gpio_set_direction() local
458 return (input == bank->is_input) ? 0 : -EINVAL; in sgpio_gpio_set_direction()
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| /drivers/leds/ |
| D | leds-tca6507.c | 162 struct bank { struct
167 } bank[3]; member
178 int bank; /* Bank used, or -1 */ member
281 static void set_code(struct tca6507_chip *tca, int reg, int bank, int new) in set_code() argument
285 if (bank) { in set_code()
298 static void set_level(struct tca6507_chip *tca, int bank, int level) in set_level() argument
300 switch (bank) { in set_level()
303 set_code(tca, TCA6507_MAX_INTENSITY, bank, level); in set_level()
309 tca->bank[bank].level = level; in set_level()
313 static void set_times(struct tca6507_chip *tca, int bank) in set_times() argument
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