| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-cs5535.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2009 Andres Salomon <dilinger@collabora.co.uk>
17 #define DRV_NAME "cs5535-gpio"
21 * 31-29,23 : reserved (always mask out)
24 * 22-16 : LPC
44 * design pattern, see Documentation/driver-api/driver-model/design-patterns.rst
51 spinlock_t lock; member
63 unsigned long addr = chip->base + 0x80 + reg; in errata_outl()
68 * non-selected bits; the recommended workaround is a in errata_outl()
69 * read-modify-write operation. in errata_outl()
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| D | gpio-ws16c48.c | 1 // SPDX-License-Identifier: GPL-2.0-only
34 * struct ws16c48_gpio - GPIO device private data structure
38 * @lock: synchronization lock to prevent I/O race conditions
47 raw_spinlock_t lock; member
53 static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset) in ws16c48_gpio_get_direction() argument
56 const unsigned port = offset / 8; in ws16c48_gpio_get_direction()
57 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_get_direction()
59 if (ws16c48gpio->io_state[port] & mask) in ws16c48_gpio_get_direction()
65 static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset) in ws16c48_gpio_direction_input() argument
68 const unsigned port = offset / 8; in ws16c48_gpio_direction_input()
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| D | gpio-max730x.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 * - DIN must be stable at the rising edge of clock.
12 * - when writing:
13 * - always clock in 16 clocks at once
14 * - at DIN: D15 first, D0 last
15 * - D0..D7 = databyte, D8..D14 = commandbyte
16 * - D15 = low -> write command
17 * - when reading
18 * - always clock in 16 clocks at once
19 * - at DIN: D15 first, D0 last
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| D | gpio-104-dio-48e.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-DIO-48E series
6 * This driver supports the following ACCES devices: 104-DIO-48E and
7 * 104-DIO-24E.
30 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
37 * struct dio48e_gpio - GPIO device private data structure
42 * @lock: synchronization lock to prevent I/O race conditions
51 raw_spinlock_t lock; member
56 static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned offset) in dio48e_gpio_get_direction() argument
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| D | gpio-gpio-mm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the Diamond Systems GPIO-MM
6 * This driver supports the following Diamond Systems devices: GPIO-MM and
7 * GPIO-MM-12.
28 MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses");
31 * struct gpiomm_gpio - GPIO device private data structure
36 * @lock: synchronization lock to prevent I/O race conditions
44 spinlock_t lock; member
49 unsigned int offset) in gpiomm_gpio_get_direction() argument
52 const unsigned int port = offset / 8; in gpiomm_gpio_get_direction()
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| D | gpio-pci-idio-16.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES PCI-IDIO-16
20 * struct idio_16_gpio_reg - GPIO device registers structure
21 * @out0_7: Read: FET Drive Outputs 0-7
22 * Write: FET Drive Outputs 0-7
23 * @in0_7: Read: Isolated Inputs 0-7
27 * @filter_ctl: Read: Activate Input Filters 0-15
28 * Write: Deactivate Input Filters 0-15
29 * @out8_15: Read: FET Drive Outputs 8-15
30 * Write: FET Drive Outputs 8-15
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| D | gpio-viperboard.c | 1 // SPDX-License-Identifier: GPL-2.0+
45 u8 offset; member
77 …"gpio-a sampling freq in Hz (default is 1000Hz) valid values: 10, 100, 1000, 10000, 100000, 100000…
79 /* ----- begin of gipo a chip -------------------------------------------- */
82 unsigned int offset) in vprbrd_gpioa_get() argument
86 struct vprbrd *vb = gpio->vb; in vprbrd_gpioa_get()
87 struct vprbrd_gpioa_msg *gamsg = (struct vprbrd_gpioa_msg *)vb->buf; in vprbrd_gpioa_get()
90 if (gpio->gpioa_out & (1 << offset)) in vprbrd_gpioa_get()
91 return !!(gpio->gpioa_val & (1 << offset)); in vprbrd_gpioa_get()
93 mutex_lock(&vb->lock); in vprbrd_gpioa_get()
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| D | gpio-sch311x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * GPIO driver for the SMSC SCH311x Super-I/O chips
20 #define DRV_NAME "gpio-sch311x"
44 spinlock_t lock; /* lock for this GPIO block */ member
93 * Super-IO functions
102 return -EBUSY; in sch311x_sio_enter()
132 static int sch311x_gpio_request(struct gpio_chip *chip, unsigned offset) in sch311x_gpio_request() argument
136 if (block->config_regs[offset] == 0) /* GPIO is not available */ in sch311x_gpio_request()
137 return -ENODEV; in sch311x_gpio_request()
139 if (!request_region(block->runtime_reg + block->config_regs[offset], in sch311x_gpio_request()
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| D | gpio-aspeed.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
43 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
56 spinlock_t lock; member
214 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
216 return gpio->base + bank->rdata_reg; in bank_reg()
218 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in bank_reg()
220 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
222 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
224 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
226 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
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| D | gpio-pl061.c | 1 // SPDX-License-Identifier: GPL-2.0-only
51 raw_spinlock_t lock; member
63 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) in pl061_get_direction() argument
67 if (readb(pl061->base + GPIODIR) & BIT(offset)) in pl061_get_direction()
73 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) in pl061_direction_input() argument
79 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_direction_input()
80 gpiodir = readb(pl061->base + GPIODIR); in pl061_direction_input()
81 gpiodir &= ~(BIT(offset)); in pl061_direction_input()
82 writeb(gpiodir, pl061->base + GPIODIR); in pl061_direction_input()
83 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_direction_input()
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| D | gpio-siox.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015-2018 Pengutronix, Uwe Kleine-König <kernel@pengutronix.de>
14 struct mutex lock; member
30 struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev); in gpio_siox_set_data()
32 mutex_lock(&ddata->lock); in gpio_siox_set_data()
33 buf[0] = ddata->setdata[0]; in gpio_siox_set_data()
34 mutex_unlock(&ddata->lock); in gpio_siox_set_data()
41 struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev); in gpio_siox_get_data()
42 size_t offset; in gpio_siox_get_data() local
45 mutex_lock(&ddata->lock); in gpio_siox_get_data()
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| D | gpio-zx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
41 raw_spinlock_t lock; member
47 static int zx_direction_input(struct gpio_chip *gc, unsigned offset) in zx_direction_input() argument
53 if (offset >= gc->ngpio) in zx_direction_input()
54 return -EINVAL; in zx_direction_input()
56 raw_spin_lock_irqsave(&chip->lock, flags); in zx_direction_input()
57 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR); in zx_direction_input()
58 gpiodir &= ~BIT(offset); in zx_direction_input()
59 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR); in zx_direction_input()
60 raw_spin_unlock_irqrestore(&chip->lock, flags); in zx_direction_input()
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| /kernel/linux/linux-4.19/drivers/gpio/ |
| D | gpio-cs5535.c | 4 * Copyright (C) 2007-2009 Andres Salomon <dilinger@collabora.co.uk>
20 #define DRV_NAME "cs5535-gpio"
24 * 31-29,23 : reserved (always mask out)
27 * 22-16 : LPC
47 * design pattern, see Documentation/driver-model/design-patterns.txt
54 spinlock_t lock; member
66 unsigned long addr = chip->base + 0x80 + reg; in errata_outl()
71 * non-selected bits; the recommended workaround is a in errata_outl()
72 * read-modify-write operation. in errata_outl()
86 static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset, in __cs5535_gpio_set() argument
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| D | gpio-ws16c48.c | 42 * struct ws16c48_gpio - GPIO device private data structure
46 * @lock: synchronization lock to prevent I/O race conditions
55 raw_spinlock_t lock; member
61 static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset) in ws16c48_gpio_get_direction() argument
64 const unsigned port = offset / 8; in ws16c48_gpio_get_direction()
65 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_get_direction()
67 return !!(ws16c48gpio->io_state[port] & mask); in ws16c48_gpio_get_direction()
70 static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset) in ws16c48_gpio_direction_input() argument
73 const unsigned port = offset / 8; in ws16c48_gpio_direction_input()
74 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_direction_input()
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| D | gpio-max730x.c | 14 * - DIN must be stable at the rising edge of clock.
15 * - when writing:
16 * - always clock in 16 clocks at once
17 * - at DIN: D15 first, D0 last
18 * - D0..D7 = databyte, D8..D14 = commandbyte
19 * - D15 = low -> write command
20 * - when reading
21 * - always clock in 16 clocks at once
22 * - at DIN: D15 first, D0 last
23 * - D0..D7 = dummy, D8..D14 = register address
[all …]
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| D | gpio-viperboard.c | 51 u8 offset; member
83 …"gpio-a sampling freq in Hz (default is 1000Hz) valid values: 10, 100, 1000, 10000, 100000, 100000…
85 /* ----- begin of gipo a chip -------------------------------------------- */
88 unsigned offset) in vprbrd_gpioa_get() argument
92 struct vprbrd *vb = gpio->vb; in vprbrd_gpioa_get()
93 struct vprbrd_gpioa_msg *gamsg = (struct vprbrd_gpioa_msg *)vb->buf; in vprbrd_gpioa_get()
96 if (gpio->gpioa_out & (1 << offset)) in vprbrd_gpioa_get()
97 return !!(gpio->gpioa_val & (1 << offset)); in vprbrd_gpioa_get()
99 mutex_lock(&vb->lock); in vprbrd_gpioa_get()
101 gamsg->cmd = VPRBRD_GPIOA_CMD_GETIN; in vprbrd_gpioa_get()
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| D | gpio-aspeed.c | 47 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
59 spinlock_t lock; member
217 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
219 return gpio->base + bank->rdata_reg; in bank_reg()
221 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in bank_reg()
223 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
225 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
227 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
229 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
231 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
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| D | gpio-pl061.c | 53 raw_spinlock_t lock; member
65 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) in pl061_get_direction() argument
69 return !(readb(pl061->base + GPIODIR) & BIT(offset)); in pl061_get_direction()
72 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) in pl061_direction_input() argument
78 raw_spin_lock_irqsave(&pl061->lock, flags); in pl061_direction_input()
79 gpiodir = readb(pl061->base + GPIODIR); in pl061_direction_input()
80 gpiodir &= ~(BIT(offset)); in pl061_direction_input()
81 writeb(gpiodir, pl061->base + GPIODIR); in pl061_direction_input()
82 raw_spin_unlock_irqrestore(&pl061->lock, flags); in pl061_direction_input()
87 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, in pl061_direction_output() argument
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| D | gpio-104-dio-48e.c | 2 * GPIO driver for the ACCES 104-DIO-48E series
14 * This driver supports the following ACCES devices: 104-DIO-48E and
15 * 104-DIO-24E.
38 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
42 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
45 * struct dio48e_gpio - GPIO device private data structure
50 * @lock: synchronization lock to prevent I/O race conditions
59 raw_spinlock_t lock; member
64 static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned offset) in dio48e_gpio_get_direction() argument
67 const unsigned port = offset / 8; in dio48e_gpio_get_direction()
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| D | gpio-zx.c | 44 raw_spinlock_t lock; member
50 static int zx_direction_input(struct gpio_chip *gc, unsigned offset) in zx_direction_input() argument
56 if (offset >= gc->ngpio) in zx_direction_input()
57 return -EINVAL; in zx_direction_input()
59 raw_spin_lock_irqsave(&chip->lock, flags); in zx_direction_input()
60 gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR); in zx_direction_input()
61 gpiodir &= ~BIT(offset); in zx_direction_input()
62 writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR); in zx_direction_input()
63 raw_spin_unlock_irqrestore(&chip->lock, flags); in zx_direction_input()
68 static int zx_direction_output(struct gpio_chip *gc, unsigned offset, in zx_direction_output() argument
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| /kernel/linux/linux-5.10/arch/mips/vr41xx/common/ |
| D | icu.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2001-2002 MontaVista Software Inc.
7 * Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
12 * - New creation, NEC VR4122 and VR4131 are supported.
13 * - Added support for NEC VR4111 and VR4121.
15 * Yoichi Yuasa <yuasa@linux-mips.org>
16 * - Coped with INTASSIGN of NEC VR4133.
84 #define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */
85 #define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */
87 #define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */
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| /kernel/linux/linux-5.10/drivers/pinctrl/sirf/ |
| D | pinctrl-sirf.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
32 #include "pinctrl-sirf.h"
34 #define DRIVER_NAME "pinmux-sirf"
39 spinlock_t lock; member
45 spinlock_t lock; member
73 struct seq_file *s, unsigned offset) in sirfsoc_pin_dbg_show() argument
106 dev_err(spmx->dev, "No child nodes passed via DT\n"); in sirfsoc_dt_node_to_map()
107 return -ENODEV; in sirfsoc_dt_node_to_map()
112 return -ENOMEM; in sirfsoc_dt_node_to_map()
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| /kernel/linux/linux-4.19/drivers/pinctrl/sirf/ |
| D | pinctrl-sirf.c | 9 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
33 #include "pinctrl-sirf.h"
35 #define DRIVER_NAME "pinmux-sirf"
40 spinlock_t lock; member
46 spinlock_t lock; member
74 struct seq_file *s, unsigned offset) in sirfsoc_pin_dbg_show() argument
107 dev_err(spmx->dev, "No child nodes passed via DT\n"); in sirfsoc_dt_node_to_map()
108 return -ENODEV; in sirfsoc_dt_node_to_map()
113 return -ENOMEM; in sirfsoc_dt_node_to_map()
154 const struct sirfsoc_muxmask *mask = mux->muxmask; in sirfsoc_pinmux_endisable()
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| /kernel/linux/linux-4.19/arch/mips/vr41xx/common/ |
| D | icu.c | 4 * Copyright (C) 2001-2002 MontaVista Software Inc.
6 * Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 * - New creation, NEC VR4122 and VR4131 are supported.
26 * - Added support for NEC VR4111 and VR4121.
28 * Yoichi Yuasa <yuasa@linux-mips.org>
29 * - Coped with INTASSIGN of NEC VR4133.
97 #define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */
98 #define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */
100 #define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */
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| /kernel/linux/linux-5.10/drivers/pinctrl/actions/ |
| D | pinctrl-owl.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
24 #include <linux/pinctrl/pinconf-generic.h>
29 #include "../pinctrl-utils.h"
30 #include "pinctrl-owl.h"
33 * struct owl_pinctrl - pinctrl state of the device
37 * @lock: spinlock to protect registers
49 raw_spinlock_t lock; member
74 tmp = readl_relaxed(pctrl->base + reg); in owl_read_field()
75 mask = (1 << width) - 1; in owl_read_field()
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