| /third_party/uboot/u-boot-2020.01/board/hisilicon/hi3519av100/ |
| D | hi3519av100_amp.c | 132 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE); in data_to_spiflash()
147 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf); in data_to_spiflash()
288 val[NUM_0] = readl(REG_BASE_GPIO4 + GPIO4_3_DATA_OFST); in is_auto_update()
289 if (val[NUM_0]) in is_auto_update()
298 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0) in is_auto_update()
321 struct mtd_info *mtd = nand_info[NUM_0]; in nand_flash_read()
365 boot_intf[NUM_0].init = NULL; in boot_medium_init()
367 boot_intf[NUM_0].read = spinor_flash_read; in boot_medium_init()
369 strncpy(boot_intf[NUM_0].name, "spinor", sizeof(boot_intf[NUM_0].name)); in boot_medium_init()
372 boot_intf[NUM_0].init = NULL; in boot_medium_init()
[all …]
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| D | hi3519av100.c | 128 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE); in data_to_spiflash()
143 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf); in data_to_spiflash()
266 val[NUM_0] = readl(REG_BASE_GPIO4 + GPIO4_3_DATA_OFST); in is_auto_update()
267 if (val[NUM_0]) in is_auto_update()
276 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0) in is_auto_update()
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| /third_party/uboot/u-boot-2020.01/board/hisilicon/hi3556av100/ |
| D | hi3556av100.c | 132 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE); in data_to_spiflash()
147 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf); in data_to_spiflash()
288 val[NUM_0] = readl(REG_BASE_GPIO4 + GPIO4_3_DATA_OFST); in is_auto_update()
289 if (val[NUM_0]) in is_auto_update()
298 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0) in is_auto_update()
321 struct mtd_info *mtd = nand_info[NUM_0]; in nand_flash_read()
364 boot_intf[NUM_0].init = NULL; in boot_medium_init()
366 boot_intf[NUM_0].read = spinor_flash_read; in boot_medium_init()
368 strncpy(boot_intf[NUM_0].name, "spinor", sizeof(boot_intf[NUM_0].name)); in boot_medium_init()
371 boot_intf[NUM_0].init = NULL; in boot_medium_init()
[all …]
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| /third_party/uboot/u-boot-2020.01/board/hisilicon/hi3518ev300/ |
| D | hi3518ev300.c | 144 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE); in data_to_spiflash()
159 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf); in data_to_spiflash()
378 val[NUM_0] = readl(REG_BASE_GPIO0 + GPIO0_0_DATA_OFST); in is_auto_update()
379 if (val[NUM_0]) in is_auto_update()
388 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0) in is_auto_update()
405 if (((uval) & (UPGRADE_STATUS_PROCESSING)) != NUM_0) { in select_upgrade_dev()
407 if (stor_dev == NUM_0) { in select_upgrade_dev()
409 target_dev = NUM_0; in select_upgrade_dev()
437 auto_update_flag = NUM_0; in misc_init_r()
443 bare_chip_program = NUM_0; in misc_init_r()
[all …]
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3519av100/ |
| D | lowlevel_init_v300.c | 190 ddrc_isvalid[NUM_0] = in ddr_scramb()
196 if (ddrc_isvalid[NUM_0]) in ddr_scramb()
204 reg_val[NUM_0] = ddrc_isvalid[NUM_0] ? in ddr_scramb()
208 } while (!(reg_val[NUM_0] & reg_val[NUM_1])); in ddr_scramb()
226 if (ddrc_isvalid[NUM_0]) in ddr_scramb()
234 reg_val[NUM_0] = ddrc_isvalid[NUM_0] ? in ddr_scramb()
238 } while (reg_val[NUM_0] | reg_val[NUM_1]); in ddr_scramb()
315 core_value[NUM_0] = 0; in get_hpm_value()
320 mda_value[NUM_0] = 0; in get_hpm_value()
325 cpu_value[NUM_0] = 0; in get_hpm_value()
[all …]
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| /third_party/uboot/u-boot-2020.01/board/hisilicon/hi3516ev300/ |
| D | hi3516ev300.c | 141 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE); in data_to_spiflash()
156 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf); in data_to_spiflash()
278 val[NUM_0] = readl(REG_BASE_GPIO0 + GPIO0_0_DATA_OFST); in is_auto_update()
279 if (val[NUM_0]) in is_auto_update()
288 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0) in is_auto_update()
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| /third_party/uboot/u-boot-2020.01/board/hisilicon/hi3516dv200/ |
| D | hi3516dv200.c | 141 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE); in data_to_spiflash()
156 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf); in data_to_spiflash()
278 val[NUM_0] = readl(REG_BASE_GPIO0 + GPIO0_0_DATA_OFST); in is_auto_update()
279 if (val[NUM_0]) in is_auto_update()
288 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0) in is_auto_update()
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| /third_party/uboot/u-boot-2020.01/board/hisilicon/hi3516av300/ |
| D | hi3516av300.c | 141 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE); in data_to_spiflash()
156 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf); in data_to_spiflash()
278 val[NUM_0] = readl(REG_BASE_GPIO0 + GPIO0_0_DATA_OFST); in is_auto_update()
279 if (val[NUM_0]) in is_auto_update()
288 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0) in is_auto_update()
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| /third_party/uboot/u-boot-2020.01/board/hisilicon/hi3516cv500/ |
| D | hi3516cv500.c | 141 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE); in data_to_spiflash()
156 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf); in data_to_spiflash()
278 val[NUM_0] = readl(REG_BASE_GPIO0 + GPIO0_0_DATA_OFST); in is_auto_update()
279 if (val[NUM_0]) in is_auto_update()
288 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0) in is_auto_update()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3569v100/ |
| D | lowlevel_init_v300.c | 184 ddrc_isvalid[NUM_0] = in ddr_scramb()
194 if (ddrc_isvalid[NUM_0]) in ddr_scramb()
208 reg_val[NUM_0] = ddrc_isvalid[NUM_0] ? (reg_get(REG_BASE_DDRC + in ddr_scramb()
216 } while (!(reg_val[NUM_0] & reg_val[NUM_1] & reg_val[NUM_2] & reg_val[NUM_3])); in ddr_scramb()
234 if (ddrc_isvalid[NUM_0]) in ddr_scramb()
248 reg_val[NUM_0] = ddrc_isvalid[NUM_0] ? (reg_get(REG_BASE_DDRC + in ddr_scramb()
256 } while (reg_val[NUM_0] | reg_val[NUM_1] | reg_val[NUM_2] | reg_val[NUM_3]); in ddr_scramb()
367 cpu_value[NUM_0] += temp & 0x3ff; in get_hpm_value()
375 mda_value[NUM_0] += temp & 0x3ff; in get_hpm_value()
383 gpu_value[NUM_0] += temp & 0x3ff; in get_hpm_value()
[all …]
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv8/hi3559av100/ |
| D | lowlevel_init_v300.c | 184 ddrc_isvalid[NUM_0] = in ddr_scramb()
194 if (ddrc_isvalid[NUM_0]) in ddr_scramb()
208 reg_val[NUM_0] = ddrc_isvalid[NUM_0] ? (reg_get(REG_BASE_DDRC + in ddr_scramb()
216 } while (!(reg_val[NUM_0] & reg_val[NUM_1] & reg_val[NUM_2] & reg_val[NUM_3])); in ddr_scramb()
234 if (ddrc_isvalid[NUM_0]) in ddr_scramb()
248 reg_val[NUM_0] = ddrc_isvalid[NUM_0] ? (reg_get(REG_BASE_DDRC + in ddr_scramb()
256 } while (reg_val[NUM_0] | reg_val[NUM_1] | reg_val[NUM_2] | reg_val[NUM_3]); in ddr_scramb()
367 cpu_value[NUM_0] += temp & 0x3ff; in get_hpm_value()
375 mda_value[NUM_0] += temp & 0x3ff; in get_hpm_value()
383 gpu_value[NUM_0] += temp & 0x3ff; in get_hpm_value()
[all …]
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| /third_party/uboot/u-boot-2020.01/board/hisilicon/hi3516ev200/ |
| D | hi3516ev200.c | 144 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE); in data_to_spiflash()
159 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf); in data_to_spiflash()
366 val[NUM_0] = readl(REG_BASE_GPIO0 + GPIO0_0_DATA_OFST); in is_auto_update()
367 if (val[NUM_0]) in is_auto_update()
376 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0) in is_auto_update()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3556av100/ |
| D | hisvb.h | 36 #ifndef NUM_0
37 #define NUM_0 0 macro
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| D | hisvb.c | 122 cpu_value[NUM_0] += temp & mask; in get_hpm_value()
130 mda_value[NUM_0] += temp & mask; in get_hpm_value()
138 core_value[NUM_0] += temp & mask; in get_hpm_value()
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| /third_party/uboot/u-boot-2020.01/board/hisilicon/hi3559av100/ |
| D | hi3559av100.c | 143 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE); in data_to_spiflash()
158 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf); in data_to_spiflash()
277 val[NUM_0] = readl(REG_BASE_GPIO0 + GPIO0_0_DATA_OFST); in is_auto_update()
278 if (val[NUM_0]) in is_auto_update()
287 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0) in is_auto_update()
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| /third_party/uboot/u-boot-2020.01/board/hisilicon/hi3516dv300/ |
| D | hi3516dv300.c | 146 val = spi_flash_erase(flash, NUM_0, UBOOT_DATA_SIZE); in data_to_spiflash()
161 val = flash->write(flash, NUM_0, UBOOT_DATA_SIZE, buf); in data_to_spiflash()
361 val[NUM_0] = readl(REG_BASE_GPIO0 + GPIO0_0_DATA_OFST); in is_auto_update()
362 if (val[NUM_0]) in is_auto_update()
371 if (val[NUM_0] == val[NUM_1] && val[NUM_1] == val[NUM_2] && val[NUM_0] == NUM_0) in is_auto_update()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3518ev300/ |
| D | pll_trainning.c | 434 regulator->steps[NUM_0] = regulator->curr + step_50; in svb_voltage_regulator_init()
436 regulator->steps[NUM_0] = regulator->max; in svb_voltage_regulator_init()
477 if (regulator->steps[NUM_0] <= regulator->steps[NUM_1]) in svb_voltage_regulator_init()
478 regulator->steps[NUM_0] = 0xffffffff; in svb_voltage_regulator_init()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev200/ |
| D | pll_trainning.c | 426 regulator->steps[NUM_0] = regulator->curr + step_50; in svb_voltage_regulator_init()
428 regulator->steps[NUM_0] = regulator->max; in svb_voltage_regulator_init()
469 if (regulator->steps[NUM_0] <= regulator->steps[NUM_1]) in svb_voltage_regulator_init()
470 regulator->steps[NUM_0] = 0xffffffff; in svb_voltage_regulator_init()
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| D | lowlevel_init_v300.c | 159 core_value[NUM_0] = 0; in get_hpm_value()
169 core_value[NUM_0] += temp & 0x3ff; in get_hpm_value()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev300/ |
| D | pll_trainning.c | 453 regulator->steps[NUM_0] = regulator->curr + step_60; in svb_voltage_regulator_init()
455 regulator->steps[NUM_0] = regulator->max; in svb_voltage_regulator_init()
496 if (regulator->steps[NUM_0] <= regulator->steps[NUM_1]) in svb_voltage_regulator_init()
497 regulator->steps[NUM_0] = 0xffffffff; in svb_voltage_regulator_init()
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| D | lowlevel_init_v300.c | 155 core_value[NUM_0] = 0; in get_hpm_value()
165 core_value[NUM_0] += temp & 0x3ff; in get_hpm_value()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516cv500/ |
| D | pll_trainning.c | 491 regulator->steps[NUM_0] = regulator->curr + step_50; in svb_voltage_regulator_init()
493 regulator->steps[NUM_0] = regulator->max; in svb_voltage_regulator_init()
518 if (regulator->steps[NUM_0] <= regulator->steps[NUM_1]) in svb_voltage_regulator_init()
519 regulator->steps[NUM_0] = 0xffffffff; in svb_voltage_regulator_init()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv200/ |
| D | pll_trainning.c | 453 regulator->steps[NUM_0] = regulator->curr + step_60; in svb_voltage_regulator_init()
455 regulator->steps[NUM_0] = regulator->max; in svb_voltage_regulator_init()
496 if (regulator->steps[NUM_0] <= regulator->steps[NUM_1]) in svb_voltage_regulator_init()
497 regulator->steps[NUM_0] = 0xffffffff; in svb_voltage_regulator_init()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv300/ |
| D | pll_trainning.c | 490 regulator->steps[NUM_0] = regulator->curr + step_50; in svb_voltage_regulator_init()
492 regulator->steps[NUM_0] = regulator->max; in svb_voltage_regulator_init()
517 if (regulator->steps[NUM_0] <= regulator->steps[NUM_1]) in svb_voltage_regulator_init()
518 regulator->steps[NUM_0] = 0xffffffff; in svb_voltage_regulator_init()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516av300/ |
| D | pll_trainning.c | 490 regulator->steps[NUM_0] = regulator->curr + step_50; in svb_voltage_regulator_init()
492 regulator->steps[NUM_0] = regulator->max; in svb_voltage_regulator_init()
517 if (regulator->steps[NUM_0] <= regulator->steps[NUM_1]) in svb_voltage_regulator_init()
518 regulator->steps[NUM_0] = 0xffffffff; in svb_voltage_regulator_init()
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