| /kernel/linux/linux-6.6/drivers/pci/controller/dwc/ |
| D | pcie-tegra194.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for the following SoCs
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
35 #include "pcie-designware.h"
37 #include <soc/tegra/bpmp-abi.h>
40 #define TEGRA194_DWC_IP_VER 0x490A
41 #define TEGRA234_DWC_IP_VER 0x562A
43 #define APPL_PINMUX 0x0
44 #define APPL_PINMUX_PEX_RST BIT(0)
50 #define APPL_CTRL 0x4
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| D | pcie-intel-gw.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Intel Gateway SoCs
20 #include "pcie-designware.h"
22 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
26 /* PCIe Application logic Registers */
27 #define PCIE_APP_CCR 0x10
28 #define PCIE_APP_CCR_LTSSM_ENABLE BIT(0)
30 #define PCIE_APP_MSG_CR 0x30
31 #define PCIE_APP_MSG_XMT_PM_TURNOFF BIT(0)
33 #define PCIE_APP_PMC 0x44
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| D | pcie-visconti.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * DWC PCIe RC driver for Toshiba Visconti ARM SoC
24 #include "pcie-designware.h"
37 #define PCIE_UL_REG_S_PCIE_MODE 0x00F4
38 #define PCIE_UL_REG_S_PCIE_MODE_EP 0x00
39 #define PCIE_UL_REG_S_PCIE_MODE_RC 0x04
41 #define PCIE_UL_REG_S_PERSTN_CTRL 0x00F8
45 #define PCIE_UL_DIRECT_PERSTN BIT(0)
50 #define PCIE_UL_REG_S_PHY_INIT_02 0x0104
51 #define PCIE_UL_PHY0_SRAM_EXT_LD_DONE BIT(0)
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| D | pcie-qcom.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
27 #include <linux/phy/pcie.h>
35 #include "pcie-designware.h"
38 #define PARF_SYS_CTRL 0x00
39 #define PARF_PM_CTRL 0x20
40 #define PARF_PCS_DEEMPH 0x34
41 #define PARF_PCS_SWING 0x38
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| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | pcie-tegra194.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra194 SoC
34 #include "pcie-designware.h"
36 #include <soc/tegra/bpmp-abi.h>
39 #define APPL_PINMUX 0x0
40 #define APPL_PINMUX_PEX_RST BIT(0)
46 #define APPL_CTRL 0x4
50 #define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0)
52 #define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST 0x1
54 #define APPL_INTR_EN_L0_0 0x8
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| /kernel/linux/linux-6.6/drivers/pci/controller/ |
| D | pci-aardvark.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
20 #include <linux/pci-ecam.h>
30 #include "../pci-bridge-emul.h"
32 /* PCIe core registers */
33 #define PCIE_CORE_DEV_ID_REG 0x0
34 #define PCIE_CORE_CMD_STATUS_REG 0x4
35 #define PCIE_CORE_DEV_REV_REG 0x8
36 #define PCIE_CORE_SSDEV_ID_REG 0x2c
37 #define PCIE_CORE_PCIEXP_CAP 0xc0
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| D | pcie-altera.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6 * Description: Altera PCIe host controller driver
23 #define RP_TX_REG0 0x2000
24 #define RP_TX_REG1 0x2004
25 #define RP_TX_CNTRL 0x2008
26 #define RP_TX_EOP 0x2
27 #define RP_TX_SOP 0x1
28 #define RP_RXCPL_STATUS 0x2010
29 #define RP_RXCPL_EOP 0x2
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| D | pci-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
52 #define AFI_AXI_BAR0_SZ 0x00
53 #define AFI_AXI_BAR1_SZ 0x04
54 #define AFI_AXI_BAR2_SZ 0x08
55 #define AFI_AXI_BAR3_SZ 0x0c
56 #define AFI_AXI_BAR4_SZ 0x10
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| D | pcie-xilinx-nwl.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
21 #include <linux/pci-ecam.h>
28 #define BRCFG_PCIE_RX0 0x00000000
29 #define BRCFG_PCIE_RX1 0x00000004
30 #define BRCFG_INTERRUPT 0x00000010
31 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
33 /* Egress - Bridge translation registers */
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| D | pcie-mediatek-gen3.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
27 #define PCIE_SETTING_REG 0x80
28 #define PCIE_PCI_IDS_1 0x9c
30 #define PCIE_RC_MODE BIT(0)
32 #define PCIE_CFGNUM_REG 0x140
33 #define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0))
37 #define PCIE_CFG_OFFSET_ADDR 0x1000
41 #define PCIE_RST_CTRL_REG 0x148
42 #define PCIE_MAC_RSTB BIT(0)
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| D | pcie-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
38 #define BRCM_PCIE_CAP_REGS 0x00ac
40 /* Broadcom STB PCIe Register Offsets */
41 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
42 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
43 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
45 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
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| D | pcie-rcar-host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
16 #include <linux/clk-provider.h>
33 #include "pcie-rcar.h"
44 /* Structure representing the PCIe interface */
46 struct rcar_pcie pcie; member
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| D | pcie-iproc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
30 #define RC_PCIE_RST_OUTPUT_SHIFT 0
32 #define PAXC_RESET_MASK 0x7f
34 #define GIC_V3_CFG_SHIFT 0
37 #define MSI_ENABLE_CFG_SHIFT 0
40 #define CFG_IND_ADDR_MASK 0x00001ffc
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| D | pcie-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Xilinx AXI PCIe Bridge
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
24 #include <linux/pci-ecam.h>
30 #define XILINX_PCIE_REG_BIR 0x00000130
31 #define XILINX_PCIE_REG_IDR 0x00000138
32 #define XILINX_PCIE_REG_IMR 0x0000013c
33 #define XILINX_PCIE_REG_PSCR 0x00000144
34 #define XILINX_PCIE_REG_RPSC 0x00000148
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | pcie-altera.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
6 * Description: Altera PCIe host controller driver
24 #define RP_TX_REG0 0x2000
25 #define RP_TX_REG1 0x2004
26 #define RP_TX_CNTRL 0x2008
27 #define RP_TX_EOP 0x2
28 #define RP_TX_SOP 0x1
29 #define RP_RXCPL_STATUS 0x2010
30 #define RP_RXCPL_EOP 0x2
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| D | pci-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for Tegra SoCs
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
51 #define AFI_AXI_BAR0_SZ 0x00
52 #define AFI_AXI_BAR1_SZ 0x04
53 #define AFI_AXI_BAR2_SZ 0x08
54 #define AFI_AXI_BAR3_SZ 0x0c
55 #define AFI_AXI_BAR4_SZ 0x10
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| D | pci-aardvark.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
28 #include "../pci-bridge-emul.h"
30 /* PCIe core registers */
31 #define PCIE_CORE_DEV_ID_REG 0x0
32 #define PCIE_CORE_CMD_STATUS_REG 0x4
33 #define PCIE_CORE_DEV_REV_REG 0x8
34 #define PCIE_CORE_PCIEXP_CAP 0xc0
35 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
45 #define PIO_BASE_ADDR 0x4000
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| D | pcie-xilinx-nwl.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
28 #define BRCFG_PCIE_RX0 0x00000000
29 #define BRCFG_INTERRUPT 0x00000010
30 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
32 /* Egress - Bridge translation registers */
33 #define E_BREG_CAPABILITIES 0x00000200
34 #define E_BREG_CONTROL 0x00000208
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| D | pcie-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
34 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
35 #define BRCM_PCIE_CAP_REGS 0x00ac
37 /* Broadcom STB PCIe Register Offsets */
38 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
39 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
40 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
42 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
43 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
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| D | pcie-iproc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
16 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
30 #define RC_PCIE_RST_OUTPUT_SHIFT 0
32 #define PAXC_RESET_MASK 0x7f
34 #define GIC_V3_CFG_SHIFT 0
37 #define MSI_ENABLE_CFG_SHIFT 0
40 #define CFG_IND_ADDR_MASK 0x00001ffc
43 #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
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| D | pcie-rcar-host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
33 #include "pcie-rcar.h"
50 /* Structure representing the PCIe interface */
52 struct rcar_pcie pcie; member
61 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
20 - enum:
21 - qcom,pcie-apq8064
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| /kernel/linux/linux-5.10/drivers/staging/mt7621-pci/ |
| D | pci-mt7621.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 * support RT2880/RT3883 PCIe
15 * support RT6855/MT7620 PCIe
39 #define MT7621_GPIO_MODE 0x60
42 #define PCIE_FTS_NUM 0x70c
44 #define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
47 #define RALINK_CLKCFG1 0x30
49 /* Host-PCI bridge registers */
50 #define RALINK_PCI_PCICFG_ADDR 0x0000
51 #define RALINK_PCI_PCIMSK_ADDR 0x000C
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| /kernel/linux/linux-6.6/drivers/pci/controller/cadence/ |
| D | pcie-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include "pcie-cadence.h"
11 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
13 u32 delay = 0x3; in cdns_pcie_detect_quiet_min_delay_set()
19 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
24 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
27 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
35 u64 sz = 1ULL << fls64(size - 1); in cdns_pcie_set_outbound_region()
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| /kernel/linux/linux-5.10/drivers/pci/controller/cadence/ |
| D | pcie-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
8 #include "pcie-cadence.h"
10 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
12 u32 delay = 0x3; in cdns_pcie_detect_quiet_min_delay_set()
18 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
23 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
26 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
34 u64 sz = 1ULL << fls64(size - 1); in cdns_pcie_set_outbound_region()
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