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Searched refs:VirtReg (Results 1 – 25 of 68) sorted by relevance

123

/external/llvm/lib/CodeGen/
DLiveRegMatrix.cpp97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument
98 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign()
100 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); in assign()
101 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, in assign()
106 Matrix[Unit].unify(VirtReg, Range); in assign()
114 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign() argument
115 unsigned PhysReg = VRM->getPhys(VirtReg.reg); in unassign()
116 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) in unassign()
118 VRM->clearVirt(VirtReg.reg); in unassign()
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DRegAllocGreedy.cpp212 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage()
213 return ExtraRegInfo[VirtReg.reg].Stage; in getStage()
216 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
218 ExtraRegInfo[VirtReg.reg].Stage = Stage; in setStage()
357 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
362 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
373 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
378 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
383 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
494 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg() argument
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DRegAllocBase.cpp85 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
86 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned"); in allocatePhysRegs()
89 if (MRI->reg_nodbg_empty(VirtReg->reg)) { in allocatePhysRegs()
90 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); in allocatePhysRegs()
91 aboutToRemoveInterval(*VirtReg); in allocatePhysRegs()
92 LIS->removeInterval(VirtReg->reg); in allocatePhysRegs()
103 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
104 << ':' << *VirtReg << " w=" << VirtReg->weight << '\n'); in allocatePhysRegs()
107 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); in allocatePhysRegs()
114 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end(); in allocatePhysRegs()
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DRegAllocFast.cpp71 unsigned VirtReg; // Virtual register number. member
77 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){} in LiveReg()
80 return TargetRegisterInfo::virtReg2Index(VirtReg); in getSparseSetIndex()
171 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
176 void killVirtReg(unsigned VirtReg);
178 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
184 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { in findLiveVirtReg() argument
185 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg()
187 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const { in findLiveVirtReg()
188 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg()
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DLiveIntervalUnion.cpp29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify() argument
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract() argument
67 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval"); in extract()
104 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const { in isSeenInterference()
106 std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg); in isSeenInterference()
130 if (VirtReg->empty() || LiveUnion->empty()) { in collectInterferingVRegs()
136 VirtRegI = VirtReg->begin(); in collectInterferingVRegs()
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DRegAllocBasic.cpp102 unsigned selectOrSplit(LiveInterval &VirtReg,
111 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences() argument
174 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in spillInterferences()
180 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight) in spillInterferences()
186 " interferences with " << VirtReg << "\n"); in spillInterferences()
220 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit() argument
226 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in selectOrSplit()
229 switch (Matrix->checkInterference(VirtReg, PhysReg)) { in selectOrSplit()
248 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) in selectOrSplit()
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DVirtRegMap.cpp82 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { in hasPreferredPhys() argument
83 unsigned Hint = MRI->getSimpleHint(VirtReg); in hasPreferredPhys()
88 return getPhys(VirtReg) == Hint; in hasPreferredPhys()
91 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { in hasKnownPreference() argument
92 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); in hasKnownPreference()
291 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); in addMBBLiveIns() local
292 if (MRI->reg_nodbg_empty(VirtReg)) in addMBBLiveIns()
294 LiveInterval &LI = LIS->getInterval(VirtReg); in addMBBLiveIns()
299 unsigned PhysReg = VRM->getPhys(VirtReg); in addMBBLiveIns()
398 unsigned VirtReg = MO.getReg(); in rewrite() local
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DLiveRegMatrix.cpp104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument
105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to " in assign()
107 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); in assign()
108 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign()
113 Matrix[Unit].unify(VirtReg, Range); in assign()
121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign() argument
122 unsigned PhysReg = VRM->getPhys(VirtReg.reg); in unassign()
123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " from " in unassign()
125 VRM->clearVirt(VirtReg.reg); in unassign()
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DRegAllocFast.cpp86 unsigned VirtReg; ///< Virtual register number. member
91 explicit LiveReg(unsigned v) : VirtReg(v) {} in LiveReg()
94 return TargetRegisterInfo::virtReg2Index(VirtReg); in getSparseSetIndex()
186 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass &RC);
191 void killVirtReg(unsigned VirtReg);
193 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
201 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { in findLiveVirtReg() argument
202 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg()
205 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const { in findLiveVirtReg()
206 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg()
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DRegAllocBasic.cpp104 unsigned selectOrSplit(LiveInterval &VirtReg,
118 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
145 bool RABasic::LRE_CanEraseVirtReg(unsigned VirtReg) { in INITIALIZE_PASS_DEPENDENCY()
146 LiveInterval &LI = LIS->getInterval(VirtReg); in INITIALIZE_PASS_DEPENDENCY()
147 if (VRM->hasPhys(VirtReg)) { in INITIALIZE_PASS_DEPENDENCY()
160 void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg() argument
161 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
165 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
205 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences() argument
213 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in spillInterferences()
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DRegAllocGreedy.cpp256 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage()
257 return ExtraRegInfo[VirtReg.reg].Stage; in getStage()
260 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
262 ExtraRegInfo[VirtReg.reg].Stage = Stage; in setStage()
466 unsigned canReassign(LiveInterval &VirtReg, unsigned PrevReg);
469 bool canEvictInterferenceInRange(LiveInterval &VirtReg, unsigned PhysReg,
473 LiveInterval &VirtReg, SlotIndex Start,
477 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
487 unsigned isSplitBenefitWorthCost(LiveInterval &VirtReg);
489 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
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DRegAllocBase.cpp89 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
90 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned"); in allocatePhysRegs()
93 if (MRI->reg_nodbg_empty(VirtReg->reg)) { in allocatePhysRegs()
94 LLVM_DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); in allocatePhysRegs()
95 aboutToRemoveInterval(*VirtReg); in allocatePhysRegs()
96 LIS->removeInterval(VirtReg->reg); in allocatePhysRegs()
107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
108 << ':' << *VirtReg << " w=" << VirtReg->weight << '\n'); in allocatePhysRegs()
113 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); in allocatePhysRegs()
120 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end(); in allocatePhysRegs()
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DLiveIntervalUnion.cpp30 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify() argument
41 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
51 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); in unify()
53 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
57 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract() argument
68 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval"); in extract()
105 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const { in isSeenInterference()
106 return is_contained(InterferingVRegs, VirtReg); in isSeenInterference()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DLiveIntervalUnion.cpp28 void LiveIntervalUnion::unify(LiveInterval &VirtReg) { in unify() argument
29 if (VirtReg.empty()) in unify()
34 LiveInterval::iterator RegPos = VirtReg.begin(); in unify()
35 LiveInterval::iterator RegEnd = VirtReg.end(); in unify()
39 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
49 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); in unify()
51 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
55 void LiveIntervalUnion::extract(LiveInterval &VirtReg) { in extract() argument
56 if (VirtReg.empty()) in extract()
61 LiveInterval::iterator RegPos = VirtReg.begin(); in extract()
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DRegAllocBasic.cpp125 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
268 LiveInterval &VirtReg = *I->second; in seedLiveRegs() local
270 PhysReg2LiveUnion[RegNum].unify(VirtReg); in seedLiveRegs()
272 enqueue(&VirtReg); in seedLiveRegs()
276 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument
277 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign()
279 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); in assign()
280 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
282 PhysReg2LiveUnion[PhysReg].unify(VirtReg); in assign()
286 void RegAllocBase::unassign(LiveInterval &VirtReg, unsigned PhysReg) { in unassign() argument
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DRegAllocGreedy.cpp138 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage()
139 return ExtraRegInfo[VirtReg.reg].Stage; in getStage()
142 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
144 ExtraRegInfo[VirtReg.reg].Stage = Stage; in setStage()
358 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg() argument
359 if (unsigned PhysReg = VRM->getPhys(VirtReg)) { in LRE_CanEraseVirtReg()
360 unassign(LIS->getInterval(VirtReg), PhysReg); in LRE_CanEraseVirtReg()
368 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg() argument
369 unsigned PhysReg = VRM->getPhys(VirtReg); in LRE_WillShrinkVirtReg()
374 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
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DVirtRegRewriter.cpp369 unsigned VirtReg; member
374 AssignedPhysReg(apr), VirtReg(vreg) {} in ReusedOp()
396 unsigned VirtReg) { in addReuse() argument
403 AssignedPhysReg, VirtReg)); in addReuse()
437 unsigned GetRegForReload(unsigned VirtReg, unsigned PhysReg, MachineInstr *MI, in GetRegForReload() argument
445 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg); in GetRegForReload()
692 unsigned VirtReg = MO.getReg(); in ReMaterialize() local
693 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) in ReMaterialize()
696 unsigned Phys = VRM.getPhys(VirtReg); in ReMaterialize()
905 MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg); in GetRegForReload()
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DLiveIntervalUnion.h92 void unify(LiveInterval &VirtReg);
95 void extract(LiveInterval &VirtReg);
112 LiveInterval *VirtReg; variable
122 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {} in Query()
125 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false), in Query()
131 VirtReg = NULL; in clear()
142 if (UserTag == UTag && VirtReg == VReg && in init()
149 VirtReg = VReg; in init()
155 assert(VirtReg && "uninitialized"); in virtReg()
156 return *VirtReg; in virtReg()
DRegAllocBase.h113 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) { in query() argument
114 Queries[PhysReg].init(UserTag, &VirtReg, &PhysReg2LiveUnion[PhysReg]); in query()
143 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
152 unsigned checkPhysRegInterference(LiveInterval& VirtReg, unsigned PhysReg);
156 void assign(LiveInterval &VirtReg, unsigned PhysReg);
161 void unassign(LiveInterval &VirtReg, unsigned PhysReg);
166 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
187 void spillReg(LiveInterval &VirtReg, unsigned PhysReg,
DRegAllocFast.cpp150 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
155 void killVirtReg(unsigned VirtReg);
157 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
165 unsigned VirtReg, unsigned Hint);
167 unsigned VirtReg, unsigned Hint);
176 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { in getStackSpaceFor() argument
178 int SS = StackSlotForVirtReg[VirtReg]; in getStackSpaceFor()
187 StackSlotForVirtReg[VirtReg] = FrameIdx; in getStackSpaceFor()
235 void RAFast::killVirtReg(unsigned VirtReg) { in killVirtReg() argument
236 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && in killVirtReg()
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DVirtRegMap.h212 bool hasPreferredPhys(unsigned VirtReg) { in hasPreferredPhys() argument
213 return getPhys(VirtReg) == getRegAllocPref(VirtReg); in hasPreferredPhys()
230 unsigned getOriginal(unsigned VirtReg) const { in getOriginal() argument
231 unsigned Orig = getPreSplitReg(VirtReg); in getOriginal()
232 return Orig ? Orig : VirtReg; in getOriginal()
449 void setIsImplicitlyDefined(unsigned VirtReg) { in setIsImplicitlyDefined() argument
450 ImplicitDefed.set(TargetRegisterInfo::virtReg2Index(VirtReg)); in setIsImplicitlyDefined()
454 bool isImplicitlyDefined(unsigned VirtReg) const { in isImplicitlyDefined() argument
455 return ImplicitDefed[TargetRegisterInfo::virtReg2Index(VirtReg)]; in isImplicitlyDefined()
460 void virtFolded(unsigned VirtReg, MachineInstr *OldMI, MachineInstr *NewMI,
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/external/llvm/include/llvm/CodeGen/
DLiveIntervalUnion.h87 void unify(LiveInterval &VirtReg, const LiveRange &Range);
88 void unify(LiveInterval &VirtReg) { in unify() argument
89 unify(VirtReg, VirtReg); in unify()
93 void extract(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg) { in extract() argument
95 extract(VirtReg, VirtReg); in extract()
113 LiveInterval *VirtReg; variable
123 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {} in Query()
126 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false), in Query()
132 VirtReg = nullptr; in clear()
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DLiveRegMatrix.h103 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
108 void assign(LiveInterval &VirtReg, unsigned PhysReg);
113 void unassign(LiveInterval &VirtReg);
128 bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg = 0);
133 bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg);
139 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned RegUnit);
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DLiveRegMatrix.h108 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
120 void assign(LiveInterval &VirtReg, unsigned PhysReg);
125 void unassign(LiveInterval &VirtReg);
140 bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg = 0);
145 bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg);
DVirtRegMap.h126 bool hasPreferredPhys(unsigned VirtReg);
131 bool hasKnownPreference(unsigned VirtReg);
147 unsigned getOriginal(unsigned VirtReg) const { in getOriginal() argument
148 unsigned Orig = getPreSplitReg(VirtReg); in getOriginal()
149 return Orig ? Orig : VirtReg; in getOriginal()

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