| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | Register.h | 20 unsigned Reg; variable
23 constexpr Register(unsigned Val = 0): Reg(Val) {} in Reg() function
24 constexpr Register(MCRegister Val): Reg(Val) {} in Register()
36 static_assert(std::numeric_limits<decltype(Reg)>::max() >= 0xFFFFFFFF,
44 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
45 return MCRegister::isStackSlot(Reg); in isStackSlot()
49 bool isStack() const { return MCRegister::isStackSlot(Reg); } in isStack()
52 static int stackSlot2Index(Register Reg) { in stackSlot2Index() argument
53 assert(Reg.isStack() && "Not a stack slot"); in stackSlot2Index()
54 return int(Reg - MCRegister::FirstStackSlot); in stackSlot2Index()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | Register.h | 20 unsigned Reg; variable
23 Register(unsigned Val = 0): Reg(Val) {} in Reg() function
24 Register(MCRegister Val): Reg(Val) {} in Register()
45 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
46 return MCRegister::isStackSlot(Reg); in isStackSlot()
50 static int stackSlot2Index(unsigned Reg) { in stackSlot2Index() argument
51 assert(isStackSlot(Reg) && "Not a stack slot"); in stackSlot2Index()
52 return int(Reg - (1u << 30)); in stackSlot2Index()
63 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
64 return MCRegister::isPhysicalRegister(Reg); in isPhysicalRegister()
[all …]
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| /external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | store.ll | 20 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
23 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
25 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
26 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
32 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
35 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
37 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
38 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
44 ; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
47 ; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
[all …]
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| D | load.ll | 21 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
24 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
26 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
27 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
33 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
36 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
38 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
39 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
45 ; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
48 ; MIPS32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
[all …]
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| D | fptosi.ll | 42 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
43 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
45 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
47 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
48 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
53 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
54 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
56 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
58 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
59 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 58 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() argument
60 VRegInfo[Reg].first = RC; in setRegClass()
63 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank() argument
65 VRegInfo[Reg].first = &RegBank; in setRegBank()
69 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass() argument
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
85 MachineRegisterInfo::constrainRegClass(Register Reg, in constrainRegClass() argument
88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
92 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs() argument
95 const LLT RegTy = getType(Reg); in constrainRegAttrs()
[all …]
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| D | AggressiveAntiDepBreaker.cpp | 70 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
71 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
83 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
84 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
85 Regs.push_back(Reg); in GetGroupRegs()
104 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) { in LeaveGroup() argument
110 GroupNodeIndices[Reg] = idx; in LeaveGroup()
114 bool AggressiveAntiDepState::IsLive(unsigned Reg) { in IsLive() argument
117 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
160 unsigned Reg = *AI; in StartBlock() local
[all …]
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| D | LiveVariables.cpp | 85 LiveVariables::VarInfo &LiveVariables::getVarInfo(Register Reg) { in getVarInfo() argument
86 assert(Reg.isVirtual() && "getVarInfo: not a virtual register!"); in getVarInfo()
87 VirtRegInfo.grow(Reg); in getVarInfo()
88 return VirtRegInfo[Reg]; in getVarInfo()
129 void LiveVariables::HandleVirtRegUse(Register Reg, MachineBasicBlock *MBB, in HandleVirtRegUse() argument
131 assert(MRI->getVRegDef(Reg) && "Register use before def!"); in HandleVirtRegUse()
135 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegUse()
166 if (MBB == MRI->getVRegDef(Reg)->getParent()) in HandleVirtRegUse()
178 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), *PI); in HandleVirtRegUse()
181 void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) { in HandleVirtRegDef() argument
[all …]
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| D | FixupStatepointCallerSaved.cpp | 96 static unsigned getRegisterSize(const TargetRegisterInfo &TRI, Register Reg) { in getRegisterSize() argument
97 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in getRegisterSize()
114 static Register performCopyPropagation(Register Reg, in performCopyPropagation() argument
119 int Idx = RI->findRegisterUseOperandIdx(Reg, false, &TRI); in performCopyPropagation()
122 return Reg; in performCopyPropagation()
126 return Reg; in performCopyPropagation()
132 if (It->readsRegister(Reg, &TRI) && !Use) in performCopyPropagation()
134 if (It->modifiesRegister(Reg, &TRI)) { in performCopyPropagation()
141 return Reg; in performCopyPropagation()
144 if (!DestSrc || DestSrc->Destination->getReg() != Reg) in performCopyPropagation()
[all …]
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| D | CriticalAntiDepBreaker.cpp | 72 unsigned Reg = *AI; in StartBlock() local
73 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
74 KillIndices[Reg] = BBSize; in StartBlock()
75 DefIndices[Reg] = ~0u; in StartBlock()
86 unsigned Reg = *I; in StartBlock() local
87 if (!IsReturnBlock && !Pristine.test(Reg)) in StartBlock()
90 unsigned Reg = *AI; in StartBlock() local
91 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
92 KillIndices[Reg] = BBSize; in StartBlock()
93 DefIndices[Reg] = ~0u; in StartBlock()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 58 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() argument
60 VRegInfo[Reg].first = RC; in setRegClass()
63 void MachineRegisterInfo::setRegBank(unsigned Reg, in setRegBank() argument
65 VRegInfo[Reg].first = &RegBank; in setRegBank()
69 constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg, in constrainRegClass() argument
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
85 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() argument
88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
92 MachineRegisterInfo::constrainRegAttrs(unsigned Reg, in constrainRegAttrs() argument
95 const LLT RegTy = getType(Reg); in constrainRegAttrs()
[all …]
|
| D | AggressiveAntiDepBreaker.cpp | 75 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
76 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
88 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
89 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
90 Regs.push_back(Reg); in GetGroupRegs()
109 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) { in LeaveGroup() argument
115 GroupNodeIndices[Reg] = idx; in LeaveGroup()
119 bool AggressiveAntiDepState::IsLive(unsigned Reg) { in IsLive() argument
122 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
165 unsigned Reg = *AI; in StartBlock() local
[all …]
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| D | CriticalAntiDepBreaker.cpp | 75 unsigned Reg = *AI; in StartBlock() local
76 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
77 KillIndices[Reg] = BBSize; in StartBlock()
78 DefIndices[Reg] = ~0u; in StartBlock()
89 unsigned Reg = *I; in StartBlock() local
90 if (!IsReturnBlock && !Pristine.test(Reg)) in StartBlock()
93 unsigned Reg = *AI; in StartBlock() local
94 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
95 KillIndices[Reg] = BBSize; in StartBlock()
96 DefIndices[Reg] = ~0u; in StartBlock()
[all …]
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| /external/llvm-project/llvm/include/llvm/MC/ |
| D | MCRegister.h | 24 unsigned Reg; variable
27 constexpr MCRegister(unsigned Val = 0): Reg(Val) {} in Reg() function
39 static_assert(std::numeric_limits<decltype(Reg)>::max() >= 0xFFFFFFFF,
50 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
51 return FirstStackSlot <= Reg && Reg < VirtualRegFlag; in isStackSlot()
56 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
57 return FirstPhysicalReg <= Reg && Reg < FirstStackSlot; in isPhysicalRegister()
61 return Reg;
71 return Reg; in id()
74 bool isValid() const { return Reg != NoRegister; } in isValid()
[all …]
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonVectorPrint.cpp | 73 static bool isVecReg(unsigned Reg) { in isVecReg() argument
74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || in isVecReg()
76 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) || in isVecReg()
77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
96 static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg, in addAsmInstr() argument
100 std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg); in addAsmInstr()
108 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) { in getInstrVecReg() argument
112 Reg = MI.getOperand(0).getReg(); in getInstrVecReg()
113 if (isVecReg(Reg)) in getInstrVecReg()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegister.h | 23 unsigned Reg; variable
26 MCRegister(unsigned Val = 0): Reg(Val) {} in Reg() function
46 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
47 return int(Reg) >= (1 << 30); in isStackSlot()
52 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
53 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); in isPhysicalRegister()
54 return int(Reg) > 0; in isPhysicalRegister()
60 return isPhysicalRegister(Reg); in isPhysical()
64 return Reg;
68 return Reg; in id()
[all …]
|
| /external/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() argument
41 VRegInfo[Reg].first = RC; in setRegClass()
44 void MachineRegisterInfo::setRegBank(unsigned Reg, in setRegBank() argument
46 VRegInfo[Reg].first = &RegBank; in setRegBank()
50 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() argument
53 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass()
62 setRegClass(Reg, NewRC); in constrainRegClass()
67 MachineRegisterInfo::recomputeRegClass(unsigned Reg) { in recomputeRegClass() argument
69 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
78 for (MachineOperand &MO : reg_nodbg_operands(Reg)) { in recomputeRegClass()
[all …]
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| D | AggressiveAntiDepBreaker.cpp | 60 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
61 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
73 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
74 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
75 Regs.push_back(Reg); in GetGroupRegs()
95 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) in LeaveGroup() argument
102 GroupNodeIndices[Reg] = idx; in LeaveGroup()
106 bool AggressiveAntiDepState::IsLive(unsigned Reg) in IsLive() argument
110 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
154 unsigned Reg = *AI; in StartBlock() local
[all …]
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| D | LiveVariables.cpp | 182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr &MI) { in HandleVirtRegDef() argument
183 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegDef()
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, in FindLastPartialDef() argument
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef()
219 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr &MI) { in HandlePhysRegUse() argument
232 MachineInstr *LastDef = PhysRegDef[Reg]; in HandlePhysRegUse()
234 if (!LastDef && !PhysRegUse[Reg]) { in HandlePhysRegUse()
244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs); in HandlePhysRegUse()
247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
[all …]
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| /external/llvm-project/llvm/test/MC/Lanai/ |
| D | memory.s | 10 ! CHECK-NEXT: <MCOperand Reg:13>
11 ! CHECK-NEXT: <MCOperand Reg:14>
18 ! CHECK-NEXT: <MCOperand Reg:13>
19 ! CHECK-NEXT: <MCOperand Reg:13>
26 ! CHECK-NEXT: <MCOperand Reg:13>
27 ! CHECK-NEXT: <MCOperand Reg:14>
34 ! CHECK-NEXT: <MCOperand Reg:13>
35 ! CHECK-NEXT: <MCOperand Reg:14>
42 ! CHECK-NEXT: <MCOperand Reg:13>
43 ! CHECK-NEXT: <MCOperand Reg:14>
[all …]
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| /external/llvm/test/MC/Lanai/ |
| D | memory.s | 10 ! CHECK-NEXT: <MCOperand Reg:13>
11 ! CHECK-NEXT: <MCOperand Reg:14>
18 ! CHECK-NEXT: <MCOperand Reg:13>
19 ! CHECK-NEXT: <MCOperand Reg:13>
26 ! CHECK-NEXT: <MCOperand Reg:13>
27 ! CHECK-NEXT: <MCOperand Reg:14>
34 ! CHECK-NEXT: <MCOperand Reg:13>
35 ! CHECK-NEXT: <MCOperand Reg:14>
42 ! CHECK-NEXT: <MCOperand Reg:13>
43 ! CHECK-NEXT: <MCOperand Reg:14>
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 78 : Reg(r), SubReg(s), Mask(m) {} in OperandMask()
79 unsigned Reg; member in __anon8074828c0111::GCNRegBankReassign::OperandMask
88 : MI(mi), Reg(reg), FreeBanks(freebanks), Weight(weight) {} in Candidate()
95 dbgs() << P->printReg(Reg) << " to banks "; in dump()
102 unsigned Reg; member in __anon8074828c0111::GCNRegBankReassign::Candidate
165 unsigned getPhysRegBank(unsigned Reg) const;
171 unsigned getRegBankMask(unsigned Reg, unsigned SubReg, int Bank);
177 unsigned Reg = AMDGPU::NoRegister, int Bank = -1);
181 bool isReassignable(unsigned Reg) const;
198 unsigned getFreeBanks(unsigned Reg, unsigned SubReg, unsigned Mask,
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonVectorPrint.cpp | 73 static bool isVecReg(unsigned Reg) { in isVecReg() argument
74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) in isVecReg()
75 || (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) in isVecReg()
76 || (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
95 static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg, in addAsmInstr() argument
99 std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg); in addAsmInstr()
107 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) { in getInstrVecReg() argument
111 Reg = MI.getOperand(0).getReg(); in getInstrVecReg()
112 if (isVecReg(Reg)) in getInstrVecReg()
117 Reg = MI.getOperand(2).getReg(); in getInstrVecReg()
[all …]
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 79 : Reg(r), SubReg(s), Mask(m) {} in OperandMask()
80 Register Reg; member in __anondebd7f180111::GCNRegBankReassign::OperandMask
89 : MI(mi), Reg(reg), SubReg(subreg), FreeBanks(freebanks) {} in Candidate()
94 dbgs() << P->printReg(Reg) << " to banks "; in dump()
101 Register Reg; member in __anondebd7f180111::GCNRegBankReassign::Candidate
184 unsigned getPhysRegBank(Register Reg, unsigned SubReg) const;
190 uint32_t getRegBankMask(Register Reg, unsigned SubReg, int Bank);
197 Register Reg = Register(),
202 bool isReassignable(Register Reg) const;
219 unsigned getFreeBanks(Register Reg, unsigned SubReg, unsigned Mask,
[all …]
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| /external/llvm-project/llvm/tools/llvm-exegesis/lib/PowerPC/ |
| D | Target.cpp | 32 std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
38 void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
54 static MCInst loadImmediate(unsigned Reg, unsigned RegBitWidth, in loadImmediate() argument
62 .addReg(Reg) in loadImmediate()
74 unsigned Reg, in fillMemoryOperands() argument
88 setMemOp(IT, MemOpIdx + 2, MCOperand::createReg(Reg)); // BaseReg in fillMemoryOperands()
92 unsigned Reg, in setRegTo() argument
98 if (PPC::GPRCRegClass.contains(Reg)) in setRegTo()
99 return {loadImmediate(Reg, 32, Value)}; in setRegTo()
100 if (PPC::G8RCRegClass.contains(Reg)) in setRegTo()
[all …]
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