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Searched refs:st1d (Results 1 – 25 of 58) sorted by relevance

123

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dst1d-diagnostics.s6 st1d z25.d, p4, [x16, #-9, MUL VL] label
12 st1d z16.d, p4, [x2, #8, MUL VL] label
20 st1d z12.d, p8, [x4, #14, MUL VL] label
25 st1d z12.d, p7.b, [x4, #14, MUL VL] label
30 st1d z12.d, p7.q, [x4, #14, MUL VL] label
38 st1d { }, p0, [x0] label
43 st1d { z1.d, z2.d }, p0, [x0] label
48 st1d { v0.2d }, p0, [x0] label
57 st1d z0.d, p0, [x0, x0] label
62 st1d z0.d, p0, [x0, xzr] label
[all …]
Dst1d.s10 st1d z0.d, p0, [x0] label
16 st1d { z0.d }, p0, [x0] label
22 st1d { z31.d }, p7, [sp, #-1, mul vl] label
28 st1d { z21.d }, p5, [x10, #5, mul vl] label
34 st1d { z0.d }, p0, [x0, x0, lsl #3] label
40 st1d { z0.d }, p0, [x0, z0.d, uxtw] label
46 st1d { z0.d }, p0, [x0, z0.d, sxtw] label
52 st1d { z0.d }, p0, [x0, z0.d, uxtw #3] label
58 st1d { z0.d }, p0, [x0, z0.d, sxtw #3] label
64 st1d { z0.d }, p0, [x0, z0.d] label
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-calling-convention-mixed.ll22 ; CHECK-NEXT: st1d { z16.d }, p0, [sp]
23 ; CHECK-NEXT: st1d { z17.d }, p0, [x8, #1, mul vl]
24 ; CHECK-NEXT: st1d { z18.d }, p0, [x8, #2, mul vl]
25 ; CHECK-NEXT: st1d { z19.d }, p0, [x8, #3, mul vl]
61 ; CHECK-NEXT: st1d { z16.d }, p0, [x9]
62 ; CHECK-NEXT: st1d { z17.d }, p0, [x8, #1, mul vl]
63 ; CHECK-NEXT: st1d { z18.d }, p0, [x8, #2, mul vl]
64 ; CHECK-NEXT: st1d { z19.d }, p0, [x8, #3, mul vl]
94 ; CHECK-NEXT: st1d { z16.d }, p0, [sp]
95 ; CHECK-NEXT: st1d { z17.d }, p0, [x8, #1, mul vl]
[all …]
Dsve-split-store.ll48 ; CHECK-NEXT: st1d { z7.d }, p0, [x0, #7, mul vl]
49 ; CHECK-NEXT: st1d { z6.d }, p0, [x0, #6, mul vl]
50 ; CHECK-NEXT: st1d { z5.d }, p0, [x0, #5, mul vl]
51 ; CHECK-NEXT: st1d { z4.d }, p0, [x0, #4, mul vl]
52 ; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl]
53 ; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl]
54 ; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl]
55 ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
120 ; CHECK-NEXT: st1d { z3.d }, p3, [x0, #3, mul vl]
121 ; CHECK-NEXT: st1d { z2.d }, p2, [x0, #2, mul vl]
[all …]
Dsve-forward-st-to-ld.ll12 ; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl]
26 ; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl]
57 ; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl]
72 ; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl]
89 ; CHECK-NEXT: st1d { z0.d }, p0, [x0, #1, mul vl]
Dsve-fixed-length-int-extends.ll58 ; CHECK-NEXT: st1d { [[A_WORDS]].d }, [[PG]], [x0]
206 ; CHECK-NEXT: st1d { [[A_DWORDS]].d }, [[PG]], [x0]
219 ; VBITS_GE_512-NEXT: st1d { [[A_DWORDS]].d }, [[PG]], [x0]
232 ; VBITS_GE_1024-NEXT: st1d { [[A_DWORDS]].d }, [[PG]], [x0]
246 ; VBITS_GE_2048-NEXT: st1d { [[A_DWORDS]].d }, [[PG]], [x1]
321 ; CHECK-NEXT: st1d { [[A_DWORDS]].d }, [[PG]], [x0]
333 ; VBITS_GE_512-NEXT: st1d { [[A_DWORDS]].d }, [[PG]], [x0]
346 ; VBITS_GE_1024-NEXT: st1d { [[A_DWORDS]].d }, [[PG]], [x1]
361 ; VBITS_GE_2048-NEXT: st1d { [[A_DWORDS]].d }, [[PG]], [x1]
378 ; CHECK-NEXT: st1d { [[A_DWORDS]].d }, [[PG]], [x0]
[all …]
Dsve-split-extract-elt.ll112 ; CHECK-NEXT: st1d { z3.d }, p0, [x8, #3, mul vl]
113 ; CHECK-NEXT: st1d { z2.d }, p0, [x8, #2, mul vl]
114 ; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl]
115 ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
209 ; CHECK-NEXT: st1d { z1.d }, p0, [x8, #1, mul vl]
210 ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
Dsve-fixed-length-fp-rounding.ll212 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
225 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
235 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
236 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
249 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
262 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
459 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
472 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
482 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
483 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
[all …]
Dsve-fixed-length-splat-vector.ll279 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x1]
291 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x1]
298 ; VBITS_EQ_256-DAG: st1d { [[RES]].d }, [[PG]], [x1]
299 ; VBITS_EQ_256-DAG: st1d { [[RES]].d }, [[PG]], [x[[B_HI]]
311 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x1]
323 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x1]
511 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
523 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
530 ; VBITS_EQ_256-DAG: st1d { [[RES]].d }, [[PG]], [x0]
531 ; VBITS_EQ_256-DAG: st1d { [[RES]].d }, [[PG]], [x[[B_HI]]
[all …]
Dsve-fixed-length-shuffles.ll39 ; VBITS_GE_512: st1d { [[LO]].d }, [[IN_PG]], [x[[LO_ADDR]]]
40 ; VBITS_GE_512: st1d { [[HI]].d }, [[IN_PG]], [x[[HI_ADDR]]]
Dsve-intrinsics-scatter-stores-64bit-scaled-offset.ll38 ; CHECK: st1d { z0.d }, p0, [x0, z1.d, lsl #3]
49 ; CHECK: st1d { z0.d }, p0, [x0, z1.d, lsl #3]
Dsve-fixed-length-fp-arith.ll244 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
261 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
278 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
295 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
493 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
508 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
523 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
538 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
748 ; CHECK: st1d { [[OP3]].d }, [[PG]], [x0]
765 ; CHECK: st1d { [[OP3]].d }, [[PG]], [x0]
[all …]
Dsve-fixed-length-fp-minmax.ll235 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
250 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
263 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
264 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
279 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
294 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
515 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
530 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
543 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
544 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
[all …]
Dsve-split-insert-elt.ll86 ; CHECK-NEXT: st1d { z3.d }, p0, [x9, #3, mul vl]
87 ; CHECK-NEXT: st1d { z2.d }, p0, [x9, #2, mul vl]
88 ; CHECK-NEXT: st1d { z1.d }, p0, [x9, #1, mul vl]
89 ; CHECK-NEXT: st1d { z0.d }, p0, [sp]
Dsve-intrinsics-scatter-stores-64bit-unscaled-offset.ll50 ; CHECK: st1d { z0.d }, p0, [x0, z1.d]
61 ; CHECK: st1d { z0.d }, p0, [x0, z1.d]
Dsve-masked-scatter-64b-scaled.ll31 ; CHECK-NEXT: st1d { z0.d }, p0, [x0, z1.d, lsl #3]
61 ; CHECK-NEXT: st1d { z0.d }, p0, [x0, z1.d, lsl #3]
Dsve-intrinsics-scatter-stores-32bit-scaled-offsets.ll134 ; CHECK: st1d { z0.d }, p0, [x0, z1.d, uxtw #3]
145 ; CHECK: st1d { z0.d }, p0, [x0, z1.d, sxtw #3]
156 ; CHECK: st1d { z0.d }, p0, [x0, z1.d, uxtw #3]
167 ; CHECK: st1d { z0.d }, p0, [x0, z1.d, sxtw #3]
Dsve-fixed-length-int-compares.ll365 ; CHECK-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
382 ; VBITS_GE_512-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
397 ; VBITS_EQ_256-DAG: st1d { [[SEXT_LO]].d }, [[PG]], [x0]
398 ; VBITS_EQ_256-DAG: st1d { [[SEXT_HI]].d }, [[PG]], [x[[A_HI]]]
415 ; VBITS_GE_1024-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
432 ; VBITS_GE_2048-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
558 ; VBITS_GE_512-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
579 ; CHECK-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
600 ; VBITS_GE_1024-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
621 ; VBITS_GE_2048-NEXT: st1d { [[SEXT]].d }, [[PG]], [x0]
Dsve-fixed-length-int-immediates.ll72 ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
140 ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
208 ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
283 ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
352 ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
424 ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
492 ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
560 ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
632 ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
704 ; CHECK-NEXT: st1d { z0.d }, p0, [x0]
[all …]
Dsve-fixed-length-int-shifts.ll334 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
349 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
362 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
363 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
378 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
393 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
713 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
728 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
741 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
742 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
[all …]
Dsve-intrinsics-scatter-stores-vector-base-imm-offset.ll100 ; CHECK: st1d { z0.d }, p0, [z1.d, #16]
111 ; CHECK: st1d { z0.d }, p0, [z1.d, #16]
221 ; CHECK-NEXT: st1d { z0.d }, p0, [x8, z1.d]
233 ; CHECK-NEXT: st1d { z0.d }, p0, [x8, z1.d]
Dsve-fixed-length-int-minmax.ll328 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
343 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
356 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
357 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
372 ; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
387 ; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
700 ; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
715 ; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
728 ; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
729 ; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
[all …]
Dsve-intrinsics-scatter-stores-32bit-unscaled-offsets.ll183 ; CHECK: st1d { z0.d }, p0, [x0, z1.d, uxtw]
194 ; CHECK: st1d { z0.d }, p0, [x0, z1.d, sxtw]
205 ; CHECK: st1d { z0.d }, p0, [x0, z1.d, uxtw]
216 ; CHECK: st1d { z0.d }, p0, [x0, z1.d, sxtw]
Dsve-fixed-length-int-log.ll357 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
374 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
391 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
408 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
684 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
699 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
714 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
729 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
1000 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
1015 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
[all …]
Dsve-fixed-length-int-arith.ll357 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
374 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
391 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
408 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
686 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
701 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
716 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
731 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
1002 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
1017 ; CHECK: st1d { [[RES]].d }, [[PG]], [x0]
[all …]

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