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Searched refs:DstReg (Results 1 – 25 of 38) sorted by relevance

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/external/llvm/lib/CodeGen/
DTwoAddressInstructionPass.cpp147 void ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
153 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
409 unsigned &SrcReg, unsigned &DstReg, in isCopyToReg() argument
412 DstReg = 0; in isCopyToReg()
414 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
417 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
423 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); in isCopyToReg()
458 unsigned SrcReg, DstReg; in isKilled() local
461 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled()
469 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { in isTwoAddrUse() argument
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DExpandPostRAPseudos.cpp53 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
69 ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg, in TransferDeadFlag() argument
73 if (MII->addRegisterDead(DstReg, TRI)) in TransferDeadFlag()
103 unsigned DstReg = MI->getOperand(0).getReg(); in LowerSubregToReg() local
109 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
111 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && in LowerSubregToReg()
123 if (DstReg != InsReg) { in LowerSubregToReg()
DRegisterCoalescer.h34 unsigned DstReg; variable
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0), in CoalescerPair()
92 unsigned getDstReg() const { return DstReg; } in getDstReg()
DOptimizePHIs.cpp87 unsigned DstReg = MI->getOperand(0).getReg(); in IsSingleValuePHICycle() local
100 if (SrcReg == DstReg) in IsSingleValuePHICycle()
130 unsigned DstReg = MI->getOperand(0).getReg(); in IsDeadPHICycle() local
131 assert(TargetRegisterInfo::isVirtualRegister(DstReg) && in IsDeadPHICycle()
142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DstReg), in IsDeadPHICycle()
DRegisterCoalescer.cpp147 unsigned DstReg, MachineInstr *CopyMI);
155 unsigned DstReg,
236 SrcReg = DstReg = SubIdx = 0; in setRegisters()
314 DstReg = Dst; in setRegisters()
320 if (SubIdx || TargetRegisterInfo::isPhysicalRegister(DstReg)) in flip()
322 std::swap(SrcReg, DstReg); in flip()
343 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { in isCoalescable()
352 return DstReg == Dst; in isCoalescable()
354 return TRI.getSubReg(DstReg, SrcSub) == Dst; in isCoalescable()
357 if (DstReg != Dst) in isCoalescable()
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DPeepholeOptimizer.cpp131 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
132 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
135 if (TargetRegisterInfo::isPhysicalRegister(DstReg) || in INITIALIZE_PASS_DEPENDENCY()
147 UI = MRI->use_nodbg_begin(DstReg); in INITIALIZE_PASS_DEPENDENCY()
226 UI = MRI->use_nodbg_begin(DstReg); in INITIALIZE_PASS_DEPENDENCY()
242 MRI->clearKillFlags(DstReg); in INITIALIZE_PASS_DEPENDENCY()
247 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
DMachineSink.cpp120 unsigned DstReg = MI->getOperand(0).getReg(); in INITIALIZE_PASS_DEPENDENCY() local
122 !TargetRegisterInfo::isVirtualRegister(DstReg) || in INITIALIZE_PASS_DEPENDENCY()
127 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
136 MRI->replaceRegWith(DstReg, SrcReg); in INITIALIZE_PASS_DEPENDENCY()
DLiveDebugVariables.cpp566 unsigned DstReg = MI->getOperand(0).getReg(); in addDefsFromCopies() local
572 if (!TargetRegisterInfo::isVirtualRegister(DstReg)) in addDefsFromCopies()
582 if (!LIS.hasInterval(DstReg)) in addDefsFromCopies()
584 LiveInterval *DstLI = &LIS.getInterval(DstReg); in addDefsFromCopies()
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp131 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
134 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
139 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
149 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
152 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
157 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
172 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
174 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
DHexagonExpandPredSpillCode.cpp121 int DstReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
122 assert(Hexagon::PredRegsRegClass.contains(DstReg) && in runOnMachineFunction()
143 DstReg).addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
152 DstReg).addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
158 DstReg).addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
/external/llvm/lib/Target/Mips/
DMipsExpandPseudo.cpp94 unsigned DstReg = I->getOperand(0).getReg(); in ExpandBuildPairF64() local
99 TM.getRegisterInfo()->getSubRegisters(DstReg); in ExpandBuildPairF64()
109 unsigned DstReg = I->getOperand(0).getReg(); in ExpandExtractElementF64() local
116 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N)); in ExpandExtractElementF64()
DMipsISelDAGToDAG.cpp190 unsigned DstReg = 0, ZeroReg = 0; in ReplaceUsesWithZeroReg() local
196 DstReg = MI.getOperand(0).getReg(); in ReplaceUsesWithZeroReg()
201 DstReg = MI.getOperand(0).getReg(); in ReplaceUsesWithZeroReg()
205 if (!DstReg) in ReplaceUsesWithZeroReg()
209 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg), in ReplaceUsesWithZeroReg()
/external/llvm/lib/Target/PTX/
DPTXInstrInfo.cpp49 unsigned DstReg, unsigned SrcReg, in copyPhysReg() argument
57 if (map[i].cls == MRI.getRegClass(DstReg)) { in copyPhysReg()
59 MachineInstr *MI = BuildMI(MBB, I, DL, MCID, DstReg). in copyPhysReg()
71 unsigned DstReg, unsigned SrcReg, in copyRegToReg() argument
81 MachineInstr *MI = BuildMI(MBB, I, DL, MCID, DstReg).addReg(SrcReg); in copyRegToReg()
90 unsigned &SrcReg, unsigned &DstReg, in isMoveInstr() argument
105 DstReg = MI.getOperand(0).getReg(); in isMoveInstr()
DPTXInstrInfo.h42 unsigned DstReg, unsigned SrcReg,
47 unsigned DstReg, unsigned SrcReg,
53 unsigned &SrcReg, unsigned &DstReg,
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp388 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD() local
390 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); in ExpandVLD()
428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
515 unsigned DstReg = 0; in ExpandLaneOp() local
519 DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandLaneOp()
520 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); in ExpandLaneOp()
569 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
616 unsigned DstReg = MI.getOperand(0).getReg(); in ExpandMOV32BitImm() local
625 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); in ExpandMOV32BitImm()
627 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
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DThumb2ITBlockPass.cpp121 unsigned DstReg = MI->getOperand(0).getReg(); in MoveCopyOutOfITBlock() local
125 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
DMLxExpansionPass.cpp209 unsigned DstReg = MI->getOperand(0).getReg(); in ExpandFPMLxInstruction() local
233 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
DARMAsmPrinter.cpp1085 unsigned SrcReg, DstReg; in EmitUnwindingInstruction() local
1093 SrcReg = DstReg = ARM::SP; in EmitUnwindingInstruction()
1096 DstReg = MI->getOperand(0).getReg(); in EmitUnwindingInstruction()
1102 assert(DstReg == ARM::SP && in EmitUnwindingInstruction()
1180 if (DstReg == FramePtr && FramePtr != ARM::SP) in EmitUnwindingInstruction()
1184 else if (DstReg == ARM::SP) { in EmitUnwindingInstruction()
1192 } else if (DstReg == ARM::SP) { in EmitUnwindingInstruction()
/external/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.cpp207 unsigned DstReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
209 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg) in eliminateFrameIndex()
210 .addReg(DstReg).addImm(-Offset); in eliminateFrameIndex()
212 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg) in eliminateFrameIndex()
213 .addReg(DstReg).addImm(Offset); in eliminateFrameIndex()
DMSP430InstrFormats.td40 def DstReg : DestMode<0>;
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
102 : IForm8<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>;
106 : IForm8<opcode, DstReg, SrcMem, Size4Bytes, outs, ins, asmstr, pattern>;
127 : IForm16<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
131 : IForm16<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>;
135 : IForm16<opcode, DstReg, SrcMem, Size4Bytes, outs, ins, asmstr, pattern>;
DMSP430InstrInfo.td165 def RET : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
229 def POP16r : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
285 def MOV8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes,
288 def MOV16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
369 def ADD8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes,
373 def ADD16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
541 def AND8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes,
545 def AND16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
619 def OR8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes,
623 def OR16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes,
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/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.h32 unsigned DstReg, int64_t Value, DebugLoc dl) const;
40 unsigned DstReg, int Offset, DebugLoc dl) const;
DXCoreRegisterInfo.cpp299 unsigned DstReg, int64_t Value, DebugLoc dl) const { in loadConstant() argument
306 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value); in loadConstant()
DXCoreFrameLowering.cpp47 unsigned DstReg, int Offset, DebugLoc dl, in loadFromStack() argument
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg) in loadFromStack()
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp132 unsigned DstReg = MI->getOperand(0).getReg(); in HandleVRSaveUpdate() local
135 if (DstReg != SrcReg) in HandleVRSaveUpdate()
136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
144 if (DstReg != SrcReg) in HandleVRSaveUpdate()
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
153 if (DstReg != SrcReg) in HandleVRSaveUpdate()
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
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