/external/llvm/lib/Target/X86/ |
D | X86InstrBuilder.h | 90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument 93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem() 98 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument 99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset() 107 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument 109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset() 114 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument 117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg() 122 addFullAddress(const MachineInstrBuilder &MIB, in addFullAddress() argument 127 MIB.addReg(AM.Base.Reg); in addFullAddress() [all …]
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D | X86InstrInfo.cpp | 1876 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), in convertToThreeAddressWithLEA() local 1882 MIB.addReg(0).addImm(1 << ShAmt) in convertToThreeAddressWithLEA() 1888 addRegOffset(MIB, leaInReg, true, 1); in convertToThreeAddressWithLEA() 1892 addRegOffset(MIB, leaInReg, true, -1); in convertToThreeAddressWithLEA() 1898 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); in convertToThreeAddressWithLEA() 1909 addRegReg(MIB, leaInReg, true, leaInReg, false); in convertToThreeAddressWithLEA() 1917 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2); in convertToThreeAddressWithLEA() 1919 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) in convertToThreeAddressWithLEA() 1922 addRegReg(MIB, leaInReg, true, leaInReg2, true); in convertToThreeAddressWithLEA() 1930 MachineInstr *NewMI = MIB; in convertToThreeAddressWithLEA() [all …]
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | InstrEmitter.cpp | 207 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument 226 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters() 241 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters() 253 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters() 295 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument 308 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand() 340 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand() 342 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand() 343 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand() 350 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand() [all …]
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D | InstrEmitter.h | 53 MachineInstrBuilder &MIB, 66 void AddRegisterOperand(MachineInstrBuilder &MIB, 77 void AddOperand(MachineInstrBuilder &MIB,
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/external/llvm/lib/Target/ARM/ |
D | ARMExpandPseudoInsts.cpp | 383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local 391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD() 400 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 403 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 404 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 407 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() 417 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD() [all …]
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D | Thumb1RegisterInfo.cpp | 130 MachineInstrBuilder MIB = in emitThumbRegPlusImmInReg() local 133 MIB = AddDefaultT1CC(MIB); in emitThumbRegPlusImmInReg() 135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg() 137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg() 138 AddDefaultPred(MIB); in emitThumbRegPlusImmInReg() 242 const MachineInstrBuilder MIB = in emitThumbRegPlusImmediate() local 245 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); in emitThumbRegPlusImmediate() 261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmediate() local 263 MIB = AddDefaultT1CC(MIB); in emitThumbRegPlusImmediate() 264 MIB.addReg(DestReg).addImm(ThisVal); in emitThumbRegPlusImmediate() [all …]
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D | ARMBaseInstrInfo.cpp | 672 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg() local 673 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 675 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 676 AddDefaultPred(MIB); in copyPhysReg() 745 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg, in AddDReg() argument 749 return MIB.addReg(Reg, State); in AddDReg() 752 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); in AddDReg() 753 return MIB.addReg(Reg, State, SubIdx); in AddDReg() 793 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD)); in storeRegToStackSlot() local 794 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot() [all …]
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D | Thumb1FrameLowering.cpp | 320 MachineInstrBuilder MIB = in emitEpilogue() local 323 AddDefaultPred(MIB); in emitEpilogue() 324 MIB.copyImplicitOps(&*MBBI); in emitEpilogue() 344 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); in spillCalleeSavedRegisters() local 345 AddDefaultPred(MIB); in spillCalleeSavedRegisters() 363 MIB.addReg(Reg, getKillRegState(isKill)); in spillCalleeSavedRegisters() 365 MIB.setMIFlags(MachineInstr::FrameSetup); in spillCalleeSavedRegisters() 383 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); in restoreCalleeSavedRegisters() local 384 AddDefaultPred(MIB); in restoreCalleeSavedRegisters() 394 (*MIB).setDesc(TII.get(ARM::tPOP_RET)); in restoreCalleeSavedRegisters() [all …]
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D | Thumb2SizeReduction.cpp | 496 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); in ReduceLoadStore() local 498 MIB.addOperand(MI->getOperand(0)); in ReduceLoadStore() 499 MIB.addOperand(MI->getOperand(1)); in ReduceLoadStore() 502 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore() 507 MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); in ReduceLoadStore() 512 MIB.addOperand(MI->getOperand(OpNum)); in ReduceLoadStore() 515 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in ReduceLoadStore() 518 MIB.setMIFlags(MI->getFlags()); in ReduceLoadStore() 520 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); in ReduceLoadStore() 556 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), in ReduceSpecial() local [all …]
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D | Thumb2InstrInfo.cpp | 157 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); in storeRegToStackSlot() local 158 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot() 159 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI); in storeRegToStackSlot() 160 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO); in storeRegToStackSlot() 161 AddDefaultPred(MIB); in storeRegToStackSlot() 198 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8)); in loadRegFromStackSlot() local 199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot() 201 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot() 202 AddDefaultPred(MIB); in loadRegFromStackSlot() [all …]
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D | ARMFastISel.cpp | 225 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); 227 const MachineInstrBuilder &MIB, 273 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { in AddOptionalDefs() argument 274 MachineInstr *MI = &*MIB; in AddOptionalDefs() 280 AddDefaultPred(MIB); in AddOptionalDefs() 287 AddDefaultT1CC(MIB); in AddOptionalDefs() 289 AddDefaultCC(MIB); in AddOptionalDefs() 291 return MIB; in AddOptionalDefs() 678 MachineInstrBuilder MIB; in ARMMaterializeGV() local 681 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) in ARMMaterializeGV() [all …]
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D | ARMBaseInstrInfo.h | 138 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg, 322 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { in AddDefaultPred() argument 323 return MIB.addImm((int64_t)ARMCC::AL).addReg(0); in AddDefaultPred() 327 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { in AddDefaultCC() argument 328 return MIB.addReg(0); in AddDefaultCC() 332 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, 334 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead)); 338 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { in AddNoT1CC() argument 339 return MIB.addReg(0); in AddNoT1CC()
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D | ARMFrameLowering.cpp | 224 MachineInstrBuilder MIB = in emitPrologue() local 228 AddDefaultCC(AddDefaultPred(MIB)); in emitPrologue() 449 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); in emitEpilogue() local 451 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), in emitEpilogue() 455 MIB.addExternalSymbol(JumpTarget.getSymbolName(), in emitEpilogue() 460 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0); in emitEpilogue() 630 MachineInstrBuilder MIB = in emitPushInst() local 634 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); in emitPushInst() 636 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), in emitPushInst() local 641 AddDefaultPred(MIB); in emitPushInst() [all …]
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D | MLxExpansionPass.cpp | 292 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction() local 296 MIB.addImm(LaneImm); in ExpandFPMLxInstruction() 297 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction() 299 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2) in ExpandFPMLxInstruction() 304 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction() 307 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction() 309 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
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D | ARMInstrInfo.cpp | 126 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL, in runOnMachineFunction() local 130 MIB.addImm(0); in runOnMachineFunction() 131 AddDefaultPred(MIB); in runOnMachineFunction()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0, 36 return MIB.addImm(Offset).addFrameIndex(FI); 38 return MIB.addFrameIndex(FI).addImm(Offset);
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/external/llvm/lib/Target/Mips/ |
D | MipsInstrInfo.cpp | 100 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); in BuildCondBr() local 104 MIB.addReg(Cond[i].getReg()); in BuildCondBr() 106 MIB.addImm(Cond[i].getImm()); in BuildCondBr() 110 MIB.addMBB(TBB); in BuildCondBr() 280 MachineInstrBuilder MIB; in genInstrWithNewOpc() local 281 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc)); in genInstrWithNewOpc() 284 MIB.addOperand(I->getOperand(J)); in genInstrWithNewOpc() 286 MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end()); in genInstrWithNewOpc() 287 return MIB; in genInstrWithNewOpc()
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D | MipsSEISelDAGToDAG.cpp | 46 MachineInstrBuilder MIB(MF, &MI); in addDSPCtrlRegOperands() local 51 MIB.addReg(Mips::DSPPos, Flag); in addDSPCtrlRegOperands() 54 MIB.addReg(Mips::DSPSCount, Flag); in addDSPCtrlRegOperands() 57 MIB.addReg(Mips::DSPCarry, Flag); in addDSPCtrlRegOperands() 60 MIB.addReg(Mips::DSPOutFlag, Flag); in addDSPCtrlRegOperands() 63 MIB.addReg(Mips::DSPCCond, Flag); in addDSPCtrlRegOperands() 66 MIB.addReg(Mips::DSPEFI, Flag); in addDSPCtrlRegOperands()
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D | MipsSEInstrInfo.cpp | 165 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg() local 168 MIB.addReg(DestReg, RegState::Define); in copyPhysReg() 171 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 174 MIB.addReg(ZeroReg); in copyPhysReg() 497 MachineInstrBuilder MIB = genInstrWithNewOpc(OpcS, I); in expandDPLoadStore() local 498 MIB->getOperand(0).setReg(LoReg); in expandDPLoadStore() 502 MIB = genInstrWithNewOpc(OpcS, I); in expandDPLoadStore() 503 MIB->getOperand(0).setReg(HiReg); in expandDPLoadStore() 504 fixDisp(MIB->getOperand(2)); in expandDPLoadStore()
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/external/llvm/lib/Target/SystemZ/ |
D | SystemZInstrBuilder.h | 27 addFrameReference(const MachineInstrBuilder &MIB, int FI) { in addFrameReference() argument 28 MachineInstr *MI = MIB; in addFrameReference() 43 return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO); in addFrameReference()
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D | SystemZFrameLowering.cpp | 110 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB, in addSavedGPR() argument 117 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive)); in addSavedGPR() 176 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG)); in spillCalleeSavedRegisters() local 179 addSavedGPR(MBB, MIB, TM, LowGPR, false); in spillCalleeSavedRegisters() 180 addSavedGPR(MBB, MIB, TM, HighGPR, false); in spillCalleeSavedRegisters() 183 MIB.addReg(SystemZ::R15D).addImm(StartOffset); in spillCalleeSavedRegisters() 190 addSavedGPR(MBB, MIB, TM, Reg, true); in spillCalleeSavedRegisters() 196 addSavedGPR(MBB, MIB, TM, SystemZ::ArgGPRs[I], true); in spillCalleeSavedRegisters() 246 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG)); in restoreCalleeSavedRegisters() local 249 MIB.addReg(LowGPR, RegState::Define); in restoreCalleeSavedRegisters() [all …]
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D | SystemZInstrInfo.cpp | 489 MachineInstrBuilder MIB = in convertToThreeAddress() local 493 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg()); in convertToThreeAddress() 496 MIB.addOperand(MI->getOperand(I)); in convertToThreeAddress() 497 return finishConvertToThreeAddress(MI, MIB, LV); in convertToThreeAddress() 524 MachineInstrBuilder MIB = in convertToThreeAddress() local 529 return finishConvertToThreeAddress(MI, MIB, LV); in convertToThreeAddress() 615 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(MemOpcode)); in foldMemoryOperandImpl() local 617 MIB.addOperand(MI->getOperand(I)); in foldMemoryOperandImpl() 618 MIB.addFrameIndex(FrameIndex).addImm(Offset); in foldMemoryOperandImpl() 620 MIB.addReg(0); in foldMemoryOperandImpl() [all …]
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/external/llvm/lib/Target/R600/ |
D | R600InstrInfo.cpp | 83 MachineInstrBuilder MIB(*MF, MI); in getMovImmInstr() local 84 MIB.addReg(DstReg, RegState::Define); in getMovImmInstr() 85 MIB.addReg(AMDGPU::ALU_LITERAL_X); in getMovImmInstr() 86 MIB.addImm(Imm); in getMovImmInstr() 87 MIB.addReg(0); // PREDICATE_BIT in getMovImmInstr() 948 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); in PredicateInstruction() local 949 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction() 1093 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode), in buildDefaultInstruction() local 1097 MIB.addImm(0) // $update_exec_mask in buildDefaultInstruction() 1100 MIB.addImm(1) // $write in buildDefaultInstruction() [all …]
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/external/llvm/lib/Target/AArch64/ |
D | AArch64FrameLowering.cpp | 214 MachineInstrBuilder MIB; in emitEpilogue() local 216 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_Bimm)); in emitEpilogue() 218 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), in emitEpilogue() 222 MIB.addExternalSymbol(JumpTarget.getSymbolName(), in emitEpilogue() 229 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_BRx)); in emitEpilogue() 230 MIB.addReg(JumpTarget.getReg(), RegState::Kill); in emitEpilogue() 236 MIB->addOperand(MBBI->getOperand(i)); in emitEpilogue()
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/external/llvm/lib/CodeGen/ |
D | MachineInstrBundle.cpp | 110 MachineInstrBuilder MIB = BuildMI(*MBB.getParent(), FirstMI->getDebugLoc(), in finalizeBundle() local 112 Bundle.prepend(MIB); in finalizeBundle() 191 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle() 200 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) | in finalizeBundle()
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