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Searched refs:ARM (Results 1 – 25 of 676) sorted by relevance

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/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp135 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
136 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
137 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
138 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
139 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
140 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
142 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
143 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,fals…
144 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
145 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,fals…
[all …]
DARMFeatures.h29 case ARM::tADC: in isV8EligibleForIT()
30 case ARM::tADDi3: in isV8EligibleForIT()
31 case ARM::tADDi8: in isV8EligibleForIT()
32 case ARM::tADDrr: in isV8EligibleForIT()
33 case ARM::tAND: in isV8EligibleForIT()
34 case ARM::tASRri: in isV8EligibleForIT()
35 case ARM::tASRrr: in isV8EligibleForIT()
36 case ARM::tBIC: in isV8EligibleForIT()
37 case ARM::tEOR: in isV8EligibleForIT()
38 case ARM::tLSLri: in isV8EligibleForIT()
[all …]
DARMBaseInstrInfo.cpp75 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
76 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
77 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
78 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
79 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
80 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
81 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
82 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
85 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
86 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
[all …]
DThumb2InstrInfo.cpp37 NopInst.setOpcode(ARM::tHINT); in getNoopForMachoTarget()
79 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
138 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass || in storeRegToStackSlot()
139 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass || in storeRegToStackSlot()
140 RC == &ARM::GPRnopcRegClass) { in storeRegToStackSlot()
141 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
147 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
152 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in storeRegToStackSlot()
[all …]
DThumb2SizeReduction.cpp63 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
64 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
65 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
66 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
67 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
68 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
69 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
70 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
71 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
74 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
[all …]
DARMInstrInfo.cpp38 NopInst.setOpcode(ARM::HINT); in getNoopForMachoTarget()
43 NopInst.setOpcode(ARM::MOVr); in getNoopForMachoTarget()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
56 case ARM::LDR_PRE_IMM: in getUnindexedOpcode()
57 case ARM::LDR_PRE_REG: in getUnindexedOpcode()
58 case ARM::LDR_POST_IMM: in getUnindexedOpcode()
59 case ARM::LDR_POST_REG: in getUnindexedOpcode()
60 return ARM::LDRi12; in getUnindexedOpcode()
61 case ARM::LDRH_PRE: in getUnindexedOpcode()
[all …]
DARMLoadStoreOptimizer.cpp165 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
176 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD; in getMemoryOpOffset()
180 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 || in getMemoryOpOffset()
181 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 || in getMemoryOpOffset()
182 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 || in getMemoryOpOffset()
183 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12) in getMemoryOpOffset()
187 if (Opcode == ARM::tLDRi || Opcode == ARM::tSTRi || in getMemoryOpOffset()
188 Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) in getMemoryOpOffset()
213 case ARM::LDRi12: in getLoadStoreMultipleOpcode()
217 case ARM_AM::ia: return ARM::LDMIA; in getLoadStoreMultipleOpcode()
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DARMCallingConv.h31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS()
75 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
76 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 }; in f64AssignAAPCS()
77 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
84 assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64"); in f64AssignAAPCS()
126 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign()
127 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
163 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
165 static const MCPhysReg SRegList[] = { ARM::S0, ARM::S1, ARM::S2, ARM::S3,
[all …]
DARMFrameLowering.cpp113 if ((MI->getOpcode() == ARM::LDR_POST_IMM || in isCSRestore()
114 MI->getOpcode() == ARM::LDR_POST_REG || in isCSRestore()
115 MI->getOpcode() == ARM::t2LDR_POST) && in isCSRestore()
117 MI->getOperand(1).getReg() == ARM::SP) in isCSRestore()
144 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
151 case ARM::VSTMDDB_UPD: in sizeOfSPAdjustment()
154 case ARM::STMDB_UPD: in sizeOfSPAdjustment()
155 case ARM::t2STMDB_UPD: in sizeOfSPAdjustment()
158 case ARM::t2STR_PRE: in sizeOfSPAdjustment()
159 case ARM::STR_PRE_IMM: in sizeOfSPAdjustment()
[all …]
DARMAsmPrinter.cpp162 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX) in runOnMachineFunction()
186 if(ARM::GPRPairRegClass.contains(Reg)) { in printOperand()
189 Reg = TRI->getSubReg(Reg, ARM::gsub_0); in printOperand()
272 if (!ARM::DPRRegClass.contains(*SR)) in PrintAsmOperand()
274 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg; in PrintAsmOperand()
299 if (ARM::GPRPairRegClass.contains(RegBegin)) { in PrintAsmOperand()
301 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand()
303 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1); in PrintAsmOperand()
350 if (RC == ARM::GPRPairRegClassID) { in PrintAsmOperand()
358 ARM::gsub_0 : ARM::gsub_1); in PrintAsmOperand()
[all …]
DARMISelDAGToDAG.cpp139 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); in SelectCMOVPred()
450 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
1249 (LHSR && LHSR->getReg() == ARM::SP)) { in SelectThumbAddrModeSP()
1483 Opcode = ARM::LDR_PRE_IMM; in SelectARMIndexedLoad()
1487 Opcode = ARM::LDR_POST_IMM; in SelectARMIndexedLoad()
1491 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG; in SelectARMIndexedLoad()
1498 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) in SelectARMIndexedLoad()
1499 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); in SelectARMIndexedLoad()
1504 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST; in SelectARMIndexedLoad()
1510 Opcode = ARM::LDRB_PRE_IMM; in SelectARMIndexedLoad()
[all …]
/external/llvm/test/CodeGen/ARM/
Dsegmented-stacks.ll1 … < %s -mtriple=arm-linux-androideabi -verify-machineinstrs | FileCheck %s -check-prefix=ARM-android
2 … %s -mtriple=arm-linux-unknown-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=ARM-linux
17 ; ARM-linux: test_basic:
19 ; ARM-linux: push {r4, r5}
20 ; ARM-linux-NEXT: mrc p15, #0, r4, c13, c0, #3
21 ; ARM-linux-NEXT: mov r5, sp
22 ; ARM-linux-NEXT: ldr r4, [r4, #4]
23 ; ARM-linux-NEXT: cmp r4, r5
24 ; ARM-linux-NEXT: blo .LBB0_2
26 ; ARM-linux: mov r4, #48
[all …]
Ddebug-frame-large-stack.ll1 …=asm -o - < %s -mtriple arm-arm-netbsd-eabi -disable-fp-elim| FileCheck %s --check-prefix=CHECK-ARM
2 …filetype=asm -o - < %s -mtriple arm-arm-netbsd-eabi | FileCheck %s --check-prefix=CHECK-ARM-FP-ELIM
9 ; CHECK-ARM-LABEL: test1:
10 ; CHECK-ARM: .cfi_startproc
11 ; CHECK-ARM: sub sp, sp, #256
12 ; CHECK-ARM: .cfi_endproc
14 ; CHECK-ARM-FP-ELIM-LABEL: test1:
15 ; CHECK-ARM-FP-ELIM: .cfi_startproc
16 ; CHECK-ARM-FP-ELIM: sub sp, sp, #256
17 ; CHECK-ARM-FP-ELIM: .cfi_endproc
[all …]
Dsegmented-stacks-dynamic.ll1 … < %s -mtriple=arm-linux-androideabi -verify-machineinstrs | FileCheck %s -check-prefix=ARM-android
2 … %s -mtriple=arm-linux-unknown-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=ARM-linux
23 ; ARM-linux: test_basic:
25 ; ARM-linux: push {r4, r5}
26 ; ARM-linux-NEXT: mrc p15, #0, r4, c13, c0, #3
27 ; ARM-linux-NEXT: mov r5, sp
28 ; ARM-linux-NEXT: ldr r4, [r4, #4]
29 ; ARM-linux-NEXT: cmp r4, r5
30 ; ARM-linux-NEXT: blo .LBB0_2
32 ; ARM-linux: mov r4, #16
[all …]
Dfast-isel-call.ll1 …abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
2 …t=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
4 …l=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=+long-calls | FileCheck %s --check-prefix=ARM-LONG
5 …namic-no-pic -mtriple=armv7-linux-gnueabi -mattr=+long-calls | FileCheck %s --check-prefix=ARM-LONG
7 …-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
8 …el=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP
41 ; ARM: foo
44 ; ARM: movw r2, #1
46 ; ARM: and r2, r2, #1
49 ; ARM: sxtb r2, r1
[all …]
Dfast-isel-intrinsic.ll1 …del=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM
2 …dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM
4 …ple=armv7-apple-ios -mattr=+long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG
5 …armv7-linux-gnueabi -mattr=+long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG
16 ; ARM-LABEL: t1:
17 ; ARM: {{(movw r0, :lower16:_?message1)|(ldr r0, .LCPI)}}
18 ; ARM: {{(movt r0, :upper16:_?message1)|(ldr r0, \[r0\])}}
19 ; ARM: add r0, r0, #5
20 ; ARM: movw r1, #64
21 ; ARM: movw r2, #10
[all …]
/external/llvm/lib/Support/
DTargetParser.cpp23 using namespace ARM;
34 ARM::FPUKind ID;
35 ARM::FPUVersion FPUVersion;
36 ARM::NeonSupportLevel NeonSupport;
37 ARM::FPURestriction Restriction;
63 ARM::ArchKind ID;
118 ARM::ArchKind ArchID;
135 StringRef llvm::ARM::getFPUName(unsigned FPUKind) { in getFPUName()
136 if (FPUKind >= ARM::FK_LAST) in getFPUName()
141 unsigned llvm::ARM::getFPUVersion(unsigned FPUKind) { in getFPUVersion()
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAsmBackend.cpp51 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
94 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { in getFixupKindInfo()
161 bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2]; in getRelaxedOpcode()
166 case ARM::tBcc: in getRelaxedOpcode()
167 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; in getRelaxedOpcode()
168 case ARM::tLDRpci: in getRelaxedOpcode()
169 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; in getRelaxedOpcode()
170 case ARM::tADR: in getRelaxedOpcode()
171 return HasThumb2 ? (unsigned)ARM::t2ADR : Op; in getRelaxedOpcode()
172 case ARM::tB: in getRelaxedOpcode()
[all …]
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp418 case ARM::HVC: { in checkDecodedInstruction()
438 assert(!STI.getFeatureBits()[ARM::ModeThumb] && in getInstruction()
575 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
577 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
582 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
596 case ARM::tBcc: in AddThumbPredicate()
597 case ARM::t2Bcc: in AddThumbPredicate()
598 case ARM::tCBZ: in AddThumbPredicate()
599 case ARM::tCBNZ: in AddThumbPredicate()
600 case ARM::tCPS: in AddThumbPredicate()
[all …]
/external/llvm/test/MC/ARM/
Ddata-in-code.ll3 ;; RUN: llvm-readobj -t | FileCheck -check-prefix=ARM %s
36 ;; ARM: Symbol {
37 ;; ARM: Name: $a
38 ;; ARM-NEXT: Value: 0x0
39 ;; ARM-NEXT: Size: 0
40 ;; ARM-NEXT: Binding: Local
41 ;; ARM-NEXT: Type: None
42 ;; ARM-NEXT: Other:
43 ;; ARM-NEXT: Section: [[MIXED_SECT:[^ ]+]]
45 ;; ARM: Symbol {
[all …]
Dvirtexts-arm.s1 …vm-mc -triple armv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-ARM
7 # CHECK-ARM: [0x71,0x00,0x40,0xe1]
8 # CHECK-ARM: [0x77,0x00,0x40,0xe1]
9 # CHECK-ARM: [0x71,0x10,0x40,0xe1]
10 # CHECK-ARM: [0x7f,0xff,0x4f,0xe1]
27 # CHECK-ARM: [0x6e,0x00,0x60,0xe1]
28 # CHECK-ARM: [0x6e,0x00,0x60,0x01]
29 # CHECK-ARM: [0x6e,0x00,0x60,0x11]
30 # CHECK-ARM: [0x6e,0x00,0x60,0x21]
31 # CHECK-ARM: [0x6e,0x00,0x60,0x31]
[all …]
Dmove-banked-regs.s1 …vm-mc -triple armv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-ARM
11 @ CHECK-ARM: mrs r2, r8_usr @ encoding: [0x00,0x22,0x00,0xe1]
12 @ CHECK-ARM: mrs r3, r9_usr @ encoding: [0x00,0x32,0x01,0xe1]
13 @ CHECK-ARM: mrs r5, r10_usr @ encoding: [0x00,0x52,0x02,0xe1]
14 @ CHECK-ARM: mrs r7, r11_usr @ encoding: [0x00,0x72,0x03,0xe1]
15 @ CHECK-ARM: mrs r11, r12_usr @ encoding: [0x00,0xb2,0x04,0xe1]
16 @ CHECK-ARM: mrs r1, sp_usr @ encoding: [0x00,0x12,0x05,0xe1]
17 @ CHECK-ARM: mrs r2, lr_usr @ encoding: [0x00,0x22,0x06,0xe1]
34 @ CHECK-ARM: mrs r2, r8_fiq @ encoding: [0x00,0x22,0x08,0xe1]
35 @ CHECK-ARM: mrs r3, r9_fiq @ encoding: [0x00,0x32,0x09,0xe1]
[all …]
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp72 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} in UnwindContext()
127 FPReg = ARM::SP; in reset()
249 return getSTI().getFeatureBits()[ARM::ModeThumb]; in isThumb()
252 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbOne()
255 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2]; in isThumbTwo()
258 return getSTI().getFeatureBits()[ARM::HasV4TOps]; in hasThumb()
261 return getSTI().getFeatureBits()[ARM::HasV6Ops]; in hasV6Ops()
264 return getSTI().getFeatureBits()[ARM::HasV6MOps]; in hasV6MOps()
267 return getSTI().getFeatureBits()[ARM::HasV7Ops]; in hasV7Ops()
270 return getSTI().getFeatureBits()[ARM::HasV8Ops]; in hasV8Ops()
[all …]
/external/llvm/test/tools/llvm-readobj/
Dsections-ext.test14 RUN: | FileCheck %s -check-prefix MACHO-ARM
722 MACHO-ARM: Sections [
723 MACHO-ARM-NEXT: Section {
724 MACHO-ARM-NEXT: Index: 0
725 MACHO-ARM-NEXT: Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00)
726 MACHO-ARM-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00)
727 MACHO-ARM-NEXT: Address: 0x0
728 MACHO-ARM-NEXT: Size: 0x3C
729 MACHO-ARM-NEXT: Offset: 664
730 MACHO-ARM-NEXT: Alignment: 2
[all …]
Dreloc-types.test9 …vm-readobj -r -expand-relocs %p/Inputs/relocs.obj.elf-arm | FileCheck %s -check-prefix ELF-ARM
15 …-readobj -r -expand-relocs %p/Inputs/relocs.obj.macho-arm | FileCheck %s -check-prefix MACHO-ARM
276 ELF-ARM: Type: R_ARM_NONE (0)
277 ELF-ARM: Type: R_ARM_PC24 (1)
278 ELF-ARM: Type: R_ARM_ABS32 (2)
279 ELF-ARM: Type: R_ARM_REL32 (3)
280 ELF-ARM: Type: R_ARM_LDR_PC_G0 (4)
281 ELF-ARM: Type: R_ARM_ABS16 (5)
282 ELF-ARM: Type: R_ARM_ABS12 (6)
283 ELF-ARM: Type: R_ARM_THM_ABS5 (7)
[all …]

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