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Searched refs:mtspr (Results 1 – 25 of 71) sorted by relevance

123

/arch/powerpc/platforms/83xx/
Dsuspend-asm.S232 mtspr SPRN_DBAT0L, r4
235 mtspr SPRN_DBAT0U, r4
242 mtspr SPRN_DBAT1L, r4
245 mtspr SPRN_DBAT1U, r4
254 mtspr SPRN_DBAT2L, r4
257 mtspr SPRN_DBAT2U, r4
272 mtspr SPRN_HID0, r3
340 mtspr SPRN_HID0, r5
390 mtspr SPRN_HID0, r5
391 mtspr SPRN_HID1, r6
[all …]
/arch/powerpc/kernel/
Dhead_8xx.S98 mtspr SPRN_SRR1,r0
101 mtspr SPRN_SRR0,r0
112 mtspr SPRN_SPRG0,r10; \
113 mtspr SPRN_SPRG1,r11; \
296 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
308 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
329 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
331 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
357 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
374 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
[all …]
Dhead_32.S40 mtspr SPRN_IBAT##n##U,RA; \
41 mtspr SPRN_DBAT##n##U,RA; \
44 mtspr SPRN_IBAT##n##U,RA; \
45 mtspr SPRN_IBAT##n##L,RB; \
49 mtspr SPRN_DBAT##n##U,RA; \
50 mtspr SPRN_DBAT##n##L,RB; \
200 mtspr SPRN_SRR1,r0
203 mtspr SPRN_SRR0,r0
243 mtspr SPRN_SPRG0,r10; \
244 mtspr SPRN_SPRG1,r11; \
[all …]
Dhead_fsl_booke.S104 mtspr SPRN_MAS6,r7
113 mtspr SPRN_MAS6,r7
121 mtspr SPRN_MAS6,r7
130 mtspr SPRN_MAS1,r7
139 mtspr SPRN_MAS0,r7
145 mtspr SPRN_MAS1,r7
166 mtspr SPRN_MAS0,r7
193 mtspr SPRN_MAS0,r7
198 mtspr SPRN_MAS1,r6
202 mtspr SPRN_MAS2,r7
[all …]
Dcpu_setup_ppc970.S34 mtspr SPRN_HID4,r3
40 mtspr SPRN_HID5,r3
49 mtspr SPRN_HID1,r0
50 mtspr SPRN_HID1,r0
56 mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
102 mtspr SPRN_HID0,r0
143 mtspr SPRN_HID4,r3
150 mtspr SPRN_HIOR,0
157 mtspr SPRN_HID0,r3
171 mtspr SPRN_HID1,r3
[all …]
Dl2cr_6xx.S130 mtspr SPRN_HID0,r4 /* Disable DPM */
168 mtspr SPRN_MSSCR0,r4
208 mtspr SPRN_L2CR,r3
221 mtspr SPRN_L2CR,r3
241 mtspr SPRN_L2CR,r3
250 mtspr SPRN_L2CR,r3
258 mtspr SPRN_MSSCR0,r3
266 mtspr 1008,r8
339 mtspr SPRN_L3CR,r3
343 mtspr SPRN_L3CR,r3
[all …]
Dhead_40x.S78 mtspr SPRN_SRR1,r0
81 mtspr SPRN_SRR0,r0
112 mtspr SPRN_SPRG0,r10; /* save two registers to work with */\
113 mtspr SPRN_SPRG1,r11; \
114 mtspr SPRN_SPRG2,r1; \
267 mtspr SPRN_SPRG0, r10 /* Save some working registers */
268 mtspr SPRN_SPRG1, r11
277 mtspr SPRN_SPRG4, r12
278 mtspr SPRN_SPRG5, r9
281 mtspr SPRN_SPRG7, r11
[all …]
Dhead_44x.S78 mtspr SPRN_CCR0,r3
114 wmmucr: mtspr SPRN_MMUCR,r3 /* Put MMUCR */
142 mtspr SPRN_PID,r0
147 mtspr SPRN_MMUCR,r5
171 mtspr SPRN_SRR1, r0
174 mtspr SPRN_SRR0,r0
229 mtspr SPRN_IVPR,r4
241 mtspr SPRN_SPRG3,r4
277 mtspr SPRN_SRR0,r4
278 mtspr SPRN_SRR1,r3
[all …]
Dcpu_setup_6xx.S71 mtspr SPRN_L2CR2,r3
90 mtspr SPRN_HID0,r8 /* enable and invalidate caches */
92 mtspr SPRN_HID0,r11 /* enable caches */
105 mtspr SPRN_HID0,r8 /* flush branch target address cache */
107 mtspr SPRN_HID0,r11
148 mtspr SPRN_MSSSR0,r11
172 mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
174 mtspr SPRN_HID0,r11
250 mtspr SPRN_ICTC,r3 /* Instruction Cache Throttling off */
252 mtspr SPRN_HID0,r11
[all …]
Dswsusp_32.S284 mtspr SPRN_DBAT4U,r4
285 mtspr SPRN_DBAT4L,r4
286 mtspr SPRN_DBAT5U,r4
287 mtspr SPRN_DBAT5L,r4
288 mtspr SPRN_DBAT6U,r4
289 mtspr SPRN_DBAT6L,r4
290 mtspr SPRN_DBAT7U,r4
291 mtspr SPRN_DBAT7L,r4
292 mtspr SPRN_IBAT4U,r4
293 mtspr SPRN_IBAT4L,r4
[all …]
Dentry_32.S155 mtspr SPRN_DBSR,r12
166 mtspr SPRN_DBCR0,r12
194 mtspr SPRN_SRR0,r11
195 mtspr SPRN_SRR1,r10
232 mtspr SPRN_SRR0,r9
233 mtspr SPRN_SRR1,r10
318 mtspr SPRN_SRR0,r7
319 mtspr SPRN_SRR1,r8
605 mtspr SPRN_SPRG3,r0 /* Update current THREAD phys addr */
615 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
[all …]
Dhead_booke.h10 mtspr SPRN_IVOR##vector_number,r26; \
14 mtspr SPRN_SPRG0,r10; /* save two registers to work with */\
15 mtspr SPRN_SPRG1,r11; \
16 mtspr SPRN_SPRG4W,r1; \
104 mtspr exc_level##_SPRG,r8; \
266 mtspr SPRN_DBSR,r10; \
272 mtspr SPRN_DSRR0,r12; \
273 mtspr SPRN_DSRR1,r9; \
276 mtspr DEBUG_SPRG,r8; \
319 mtspr SPRN_DBSR,r10; \
[all …]
/arch/powerpc/include/asm/
Doprofile_impl.h104 mtspr(SPRN_PMC1, val); in classic_ctr_write()
107 mtspr(SPRN_PMC2, val); in classic_ctr_write()
110 mtspr(SPRN_PMC3, val); in classic_ctr_write()
113 mtspr(SPRN_PMC4, val); in classic_ctr_write()
116 mtspr(SPRN_PMC5, val); in classic_ctr_write()
119 mtspr(SPRN_PMC6, val); in classic_ctr_write()
125 mtspr(SPRN_PMC7, val); in classic_ctr_write()
128 mtspr(SPRN_PMC8, val); in classic_ctr_write()
Dtime.h140 mtspr(SPRN_TBWL, 0); in set_tb()
141 mtspr(SPRN_TBWU, upper); in set_tb()
142 mtspr(SPRN_TBWL, lower); in set_tb()
168 mtspr(SPRN_PIT, val); in set_dec()
184 mtspr(SPRN_DEC, val); in set_dec()
Dexception.h75 mtspr SPRN_SRR0,r12; \
77 mtspr SPRN_SRR1,r10; \
147 mtspr SPRN_SPRG1,r13; /* save r13 */ \
155 mtspr SPRN_SPRG1,r20; /* save r20 */ \
157 mtspr SPRN_SRR0,r20; \
159 mtspr SPRN_SRR1,r20; \
161 mtspr SPRN_SPRG1,r13; /* save r13 */ \
170 mtspr SPRN_SPRG1,r13; /* save r13 */ \
186 mtspr SPRN_SRR0,r12; \
188 mtspr SPRN_SRR1,r10; \
/arch/powerpc/platforms/powermac/
Dcache.S63 mtspr SPRN_HID0,r4 /* Disable DPM */
91 mtspr SPRN_HID0,r3
97 mtspr SPRN_HID0,r3
99 mtspr SPRN_HID0,r3
109 1: mtspr SPRN_L2CR,r3
143 1: mtspr SPRN_L2CR,r5
155 mtspr SPRN_L2CR,r4
167 mtspr SPRN_L2CR,r4
173 mtspr SPRN_HID0,r0
181 mtspr SPRN_HID0,r0
[all …]
Dsleep.S193 mtspr SPRN_HID0,r2
225 mtspr SPRN_HID0,r3
329 mtspr SPRN_DBAT4U,r4
330 mtspr SPRN_DBAT4L,r4
331 mtspr SPRN_DBAT5U,r4
332 mtspr SPRN_DBAT5L,r4
333 mtspr SPRN_DBAT6U,r4
334 mtspr SPRN_DBAT6L,r4
335 mtspr SPRN_DBAT7U,r4
336 mtspr SPRN_DBAT7L,r4
[all …]
/arch/powerpc/oprofile/
Dop_model_pa6t.c67 mtspr(SPRN_PA6T_PMC0, val); in ctr_write()
70 mtspr(SPRN_PA6T_PMC1, val); in ctr_write()
73 mtspr(SPRN_PA6T_PMC2, val); in ctr_write()
76 mtspr(SPRN_PA6T_PMC3, val); in ctr_write()
79 mtspr(SPRN_PA6T_PMC4, val); in ctr_write()
82 mtspr(SPRN_PA6T_PMC5, val); in ctr_write()
150 mtspr(SPRN_PA6T_MMCR0, mmcr0); in pa6t_cpu_setup()
153 mtspr(SPRN_PA6T_MMCR1, mmcr1); in pa6t_cpu_setup()
176 mtspr(SPRN_PA6T_MMCR0, mmcr0); in pa6t_start()
192 mtspr(SPRN_PA6T_MMCR0, mmcr0); in pa6t_stop()
[all …]
Dop_model_rs64.c77 mtspr(SPRN_MMCR0, tmp); in ctrl_write()
80 mtspr(SPRN_MMCR1, tmp); in ctrl_write()
112 mtspr(SPRN_MMCR0, mmcr0); in rs64_cpu_setup()
115 mtspr(SPRN_MMCR1, 0); in rs64_cpu_setup()
118 mtspr(SPRN_MMCRA, 0); in rs64_cpu_setup()
123 mtspr(SPRN_MMCR0, mmcr0); in rs64_cpu_setup()
158 mtspr(SPRN_MMCR0, mmcr0); in rs64_start()
171 mtspr(SPRN_MMCR0, mmcr0); in rs64_stop()
215 mtspr(SPRN_MMCR0, mmcr0); in rs64_handle_interrupt()
Dop_model_power4.c98 mtspr(SPRN_MMCR0, mmcr0); in power4_cpu_setup()
102 mtspr(SPRN_MMCR0, mmcr0); in power4_cpu_setup()
104 mtspr(SPRN_MMCR1, mmcr1_val); in power4_cpu_setup()
108 mtspr(SPRN_MMCRA, mmcra); in power4_cpu_setup()
150 mtspr(SPRN_MMCR0, mmcr0); in power4_start()
165 mtspr(SPRN_MMCR0, mmcr0); in power4_stop()
300 mtspr(SPRN_MMCRA, mmcra); in power4_handle_interrupt()
308 mtspr(SPRN_MMCR0, mmcr0); in power4_handle_interrupt()
Dop_model_7450.c68 mtspr(SPRN_MMCR0, mmcr0); in pmc_start_ctrs()
79 mtspr(SPRN_MMCR0, mmcr0); in pmc_stop_ctrs()
89 mtspr(SPRN_MMCR0, mmcr0_val); in fsl7450_cpu_setup()
90 mtspr(SPRN_MMCR1, mmcr1_val); in fsl7450_cpu_setup()
91 mtspr(SPRN_MMCR2, mmcr2_val); in fsl7450_cpu_setup()
/arch/powerpc/kvm/
D44x.c46 mtspr(SPRN_IAC1, vcpu->arch.host_iac[0]); in kvmppc_core_load_host_debugstate()
47 mtspr(SPRN_IAC2, vcpu->arch.host_iac[1]); in kvmppc_core_load_host_debugstate()
48 mtspr(SPRN_IAC3, vcpu->arch.host_iac[2]); in kvmppc_core_load_host_debugstate()
49 mtspr(SPRN_IAC4, vcpu->arch.host_iac[3]); in kvmppc_core_load_host_debugstate()
50 mtspr(SPRN_DBCR1, vcpu->arch.host_dbcr1); in kvmppc_core_load_host_debugstate()
51 mtspr(SPRN_DBCR2, vcpu->arch.host_dbcr2); in kvmppc_core_load_host_debugstate()
52 mtspr(SPRN_DBCR0, vcpu->arch.host_dbcr0); in kvmppc_core_load_host_debugstate()
76 mtspr(SPRN_IAC1, dbg->bp[0]); in kvmppc_core_load_guest_debugstate()
80 mtspr(SPRN_IAC2, dbg->bp[1]); in kvmppc_core_load_guest_debugstate()
84 mtspr(SPRN_IAC3, dbg->bp[2]); in kvmppc_core_load_guest_debugstate()
[all …]
/arch/powerpc/mm/
Dtlb_nohash_low.S49 mtspr SPRN_PID,r4
51 mtspr SPRN_PID,r6
88 mtspr SPRN_MMUCR,r5
135 mtspr SPRN_MMUCSR0, r3
152 mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
158 mtspr SPRN_MAS1,r4
D40x_mmu.c71 mtspr(SPRN_ZPR, 0x10000000); in MMU_init_hw()
80 mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */ in MMU_init_hw()
87 mtspr(SPRN_DCCR, 0xF0000000); /* 512 MB of data space at 0x0. */ in MMU_init_hw()
88 mtspr(SPRN_ICCR, 0xF0000000); /* 512 MB of instr. space at 0x0. */ in MMU_init_hw()
/arch/powerpc/platforms/86xx/
Dsbc8641d.c93 mtspr(SPRN_TBWL, 0); in mpc86xx_time_init()
94 mtspr(SPRN_TBWU, 0); in mpc86xx_time_init()
98 mtspr(SPRN_HID0, temp); in mpc86xx_time_init()

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