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/drivers/scsi/
Dnsp32.h92 # define IRQSTATUS_LATCHED_MSG BIT(0)
93 # define IRQSTATUS_LATCHED_IO BIT(1)
94 # define IRQSTATUS_LATCHED_CD BIT(2)
95 # define IRQSTATUS_LATCHED_BUS_FREE BIT(3)
96 # define IRQSTATUS_RESELECT_OCCUER BIT(4)
97 # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
98 # define IRQSTATUS_SCSIRESET_IRQ BIT(6)
99 # define IRQSTATUS_TIMER_IRQ BIT(7)
100 # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)
101 # define IRQSTATUS_PCI_IRQ BIT(9)
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/drivers/net/wireless/rtlwifi/rtl8192se/
Dreg.h327 #define RXDMA_AGG_EN BIT(7)
333 #define ISO_MD2PP BIT(0)
334 #define ISO_PA2PCIE BIT(3)
335 #define ISO_PLL2MD BIT(4)
336 #define ISO_PWC_DV2RP BIT(11)
337 #define ISO_PWC_RV2RP BIT(12)
340 #define FEN_MREGEN BIT(15)
341 #define FEN_DCORE BIT(11)
342 #define FEN_CPUEN BIT(10)
344 #define PAD_HWPD_IDN BIT(22)
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/drivers/net/ethernet/atheros/alx/
Dreg.h61 #define ALX_UE_SVRT_FCPROTERR BIT(13)
62 #define ALX_UE_SVRT_DLPROTERR BIT(4)
66 #define ALX_EFLD_F_EXIST BIT(10)
67 #define ALX_EFLD_E_EXIST BIT(9)
68 #define ALX_EFLD_STAT BIT(5)
69 #define ALX_EFLD_START BIT(0)
73 #define ALX_SLD_STAT BIT(12)
74 #define ALX_SLD_START BIT(11)
78 #define ALX_PDLL_TRNS1_D3PLLOFF_EN BIT(11)
81 #define ALX_PMCTRL_HOTRST_WTEN BIT(31)
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/drivers/net/wireless/rtlwifi/rtl8192de/
Dreg.h94 #define MAC0_ON BIT(7)
95 #define MAC1_ON BIT(0)
96 #define MAC0_READY BIT(0)
97 #define MAC1_READY BIT(0)
442 #define RATE_1M BIT(0)
443 #define RATE_2M BIT(1)
444 #define RATE_5_5M BIT(2)
445 #define RATE_11M BIT(3)
447 #define RATE_6M BIT(4)
448 #define RATE_9M BIT(5)
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/drivers/net/wireless/rtlwifi/rtl8188ee/
Dreg.h381 #define CMDEEPROM_EN BIT(5)
382 #define CMDEEPROM_SEL BIT(4)
383 #define CMD9346CR_9356SEL BIT(4)
388 #define GPIOSEL_ENBT BIT(5)
396 #define HSIMR_GPIO12_0_INT_EN BIT(0)
397 #define HSIMR_SPS_OCP_INT_EN BIT(5)
398 #define HSIMR_RON_INT_EN BIT(6)
399 #define HSIMR_PDN_INT_EN BIT(7)
400 #define HSIMR_GPIO9_INT_EN BIT(25)
404 #define HSISR_GPIO12_0_INT BIT(0)
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Dpwrseq.h73 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
76 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0}, \
79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
82 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
85 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0}, \
88 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
91 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*LDO normal mode*/\
95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*SDIO Driving*/\
103 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*LDO Sleep mode*/\
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/drivers/net/wireless/rtlwifi/rtl8723ae/
Dreg.h346 #define CMDEEPROM_EN BIT(5)
347 #define CMDEEPROM_SEL BIT(4)
348 #define CMD9346CR_9356SEL BIT(4)
353 #define GPIOSEL_ENBT BIT(5)
371 #define RRSR_1M BIT(0)
372 #define RRSR_2M BIT(1)
373 #define RRSR_5_5M BIT(2)
374 #define RRSR_11M BIT(3)
375 #define RRSR_6M BIT(4)
376 #define RRSR_9M BIT(5)
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Dpwrseq.h72 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), 0}, \
75 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
78 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
81 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
84 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
87 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
90 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}
100 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
102 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
104 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}
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Dhal_bt_coexist.h50 #define BT_COEX_STATE_BT30 BIT(0)
51 #define BT_COEX_STATE_WIFI_HT20 BIT(1)
52 #define BT_COEX_STATE_WIFI_HT40 BIT(2)
53 #define BT_COEX_STATE_WIFI_LEGACY BIT(3)
55 #define BT_COEX_STATE_WIFI_RSSI_LOW BIT(4)
56 #define BT_COEX_STATE_WIFI_RSSI_MEDIUM BIT(5)
57 #define BT_COEX_STATE_WIFI_RSSI_HIGH BIT(6)
58 #define BT_COEX_STATE_DEC_BT_POWER BIT(7)
60 #define BT_COEX_STATE_WIFI_IDLE BIT(8)
61 #define BT_COEX_STATE_WIFI_UPLINK BIT(9)
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/drivers/net/wireless/rtlwifi/rtl8192ce/
Dreg.h360 #define CMDEEPROM_EN BIT(5)
361 #define CMDEEPROM_SEL BIT(4)
362 #define CMD9346CR_9356SEL BIT(4)
367 #define GPIOSEL_ENBT BIT(5)
385 #define RRSR_1M BIT(0)
386 #define RRSR_2M BIT(1)
387 #define RRSR_5_5M BIT(2)
388 #define RRSR_11M BIT(3)
389 #define RRSR_6M BIT(4)
390 #define RRSR_9M BIT(5)
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/drivers/staging/rtl8712/
Drtl8712_cmdctrl_bitdef.h28 #define _APSDOFF_STATUS BIT(15)
29 #define _APSDOFF BIT(14)
30 #define _BBRSTn BIT(13) /*Enable OFDM/CCK*/
31 #define _BB_GLB_RSTn BIT(12) /*Enable BB*/
32 #define _SCHEDULE_EN BIT(10) /*Enable MAC scheduler*/
33 #define _MACRXEN BIT(9)
34 #define _MACTXEN BIT(8)
35 #define _DDMA_EN BIT(7) /*FW off load function enable*/
36 #define _FW2HW_EN BIT(6) /*MAC every module reset */
37 #define _RXDMA_EN BIT(5)
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Drtl8712_fifoctrl_bitdef.h30 #define _TXSTATUS_OVF BIT(15)
33 #define _STATUSFF1_OVF BIT(7)
34 #define _STATUSFF1_EMPTY BIT(6)
35 #define _STATUSFF0_OVF BIT(5)
36 #define _STATUSFF0_EMPTY BIT(4)
37 #define _RXFF1_OVF BIT(3)
38 #define _RXFF1_EMPTY BIT(2)
39 #define _RXFF0_OVF BIT(1)
40 #define _RXFF0_EMPTY BIT(0)
58 #define _C2HFF_POLL BIT(4)
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Drtl8712_syscfg_bitdef.h36 #define iso_LDR2RP BIT(iso_LDR2RP_SHT) /* 1:isolation, 0:attach*/
40 #define FEN_DIO_SDIO BIT(FEN_DIO_SDIO_SHT)
42 #define FEN_SDIO BIT(FEN_SDIO_SHT)
44 #define FEN_USBA BIT(FEN_USBA_SHT)
46 #define FEN_UPLL BIT(FEN_UPLL_SHT)
48 #define FEN_USBD BIT(FEN_USBD_SHT)
50 #define FEN_DIO_PCIE BIT(FEN_DIO_PCIE_SHT)
52 #define FEN_PCIEA BIT(FEN_PCIEA_SHT)
54 #define FEN_PPLL BIT(FEN_PPLL_SHT)
56 #define FEN_PCIED BIT(FEN_PCIED_SHT)
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Dwifi.h31 #ifdef BIT
32 #undef BIT
34 #define BIT(x) (1 << (x)) macro
61 WIFI_CTRL_TYPE = (BIT(2)),
62 WIFI_DATA_TYPE = (BIT(3)),
63 WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), /*!< QoS Data */
69 WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE),
70 WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE),
71 WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE),
72 WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE),
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Drtl8712_interrupt_bitdef.h25 #define _CPUERR BIT(29)
26 #define _ATIMEND BIT(28)
27 #define _TXBCNOK BIT(27)
28 #define _TXBCNERR BIT(26)
29 #define _BCNDMAINT4 BIT(25)
30 #define _BCNDMAINT3 BIT(24)
31 #define _BCNDMAINT2 BIT(23)
32 #define _BCNDMAINT1 BIT(22)
33 #define _BCNDOK4 BIT(21)
34 #define _BCNDOK3 BIT(20)
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/drivers/net/ethernet/atheros/atl1c/
Datl1c_hw.h108 #define TWSI_CTRL_LD_EXIST BIT(23)
109 #define TWSI_CTRL_HW_LDSTAT BIT(12) /* 0:finish,1:in progress */
110 #define TWSI_CTRL_SW_LDSTART BIT(11)
122 #define PCIE_PHYMISC_FORCE_RCV_DET BIT(2)
135 #define TWSI_DEBUG_DEV_EXIST BIT(29)
138 #define DMA_DBG_VENDOR_MSG BIT(0)
151 #define OTP_CTRL_CLK_EN BIT(1)
154 #define PM_CTRL_HOTRST BIT(31)
155 #define PM_CTRL_MAC_ASPM_CHK BIT(30) /* L0s/L1 dis by MAC based on
157 #define PM_CTRL_SA_DLY_EN BIT(29)
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/drivers/usb/chipidea/
Dbits.h19 #define HCCPARAMS_LEN BIT(17)
23 #define DCCPARAMS_DC BIT(7)
24 #define DCCPARAMS_HC BIT(8)
27 #define TESTMODE_FORCE BIT(0)
30 #define USBCMD_RS BIT(0)
31 #define USBCMD_RST BIT(1)
32 #define USBCMD_SUTW BIT(13)
33 #define USBCMD_ATDTW BIT(14)
36 #define USBi_UI BIT(0)
37 #define USBi_UEI BIT(1)
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/drivers/net/wireless/rtlwifi/
Ddebug.h79 #define COMP_ERR BIT(0)
80 #define COMP_FW BIT(1)
81 #define COMP_INIT BIT(2) /*For init/deinit */
82 #define COMP_RECV BIT(3) /*For Rx. */
83 #define COMP_SEND BIT(4) /*For Tx. */
84 #define COMP_MLME BIT(5) /*For MLME. */
85 #define COMP_SCAN BIT(6) /*For Scan. */
86 #define COMP_INTR BIT(7) /*For interrupt Related. */
87 #define COMP_LED BIT(8) /*For LED. */
88 #define COMP_SEC BIT(9) /*For sec. */
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/drivers/mmc/host/
Ddw_mmc.h69 #define SDMMC_CTRL_USE_IDMAC BIT(25)
70 #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
71 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
72 #define SDMMC_CTRL_SEND_CCSD BIT(9)
73 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
74 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
75 #define SDMMC_CTRL_READ_WAIT BIT(6)
76 #define SDMMC_CTRL_DMA_ENABLE BIT(5)
77 #define SDMMC_CTRL_INT_ENABLE BIT(4)
78 #define SDMMC_CTRL_DMA_RESET BIT(2)
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/drivers/net/wireless/ath/carl9170/
Dhw.h115 #define AR9170_MAC_INT_TXC BIT(0)
116 #define AR9170_MAC_INT_RXC BIT(1)
117 #define AR9170_MAC_INT_RETRY_FAIL BIT(2)
118 #define AR9170_MAC_INT_WAKEUP BIT(3)
119 #define AR9170_MAC_INT_ATIM BIT(4)
120 #define AR9170_MAC_INT_DTIM BIT(5)
121 #define AR9170_MAC_INT_CFG_BCN BIT(6)
122 #define AR9170_MAC_INT_ABORT BIT(7)
123 #define AR9170_MAC_INT_QOS BIT(8)
124 #define AR9170_MAC_INT_MIMO_PS BIT(9)
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/drivers/scsi/pcmcia/
Dnsp_cs.h40 # define IRQCONTROL_RESELECT_CLEAR BIT(0)
41 # define IRQCONTROL_PHASE_CHANGE_CLEAR BIT(1)
42 # define IRQCONTROL_TIMER_CLEAR BIT(2)
43 # define IRQCONTROL_FIFO_CLEAR BIT(3)
52 # define IRQSTATUS_SCSI BIT(0)
53 # define IRQSTATUS_TIMER BIT(2)
54 # define IRQSTATUS_FIFO BIT(3)
58 # define IF_IFSEL BIT(0)
59 # define IF_REGSEL BIT(2)
64 # define FIFOSTATUS_FULL_EMPTY BIT(7)
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/drivers/pinctrl/
Dpinctrl-sirf.c229 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
230 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
231 BIT(17) | BIT(18),
234 .mask = BIT(31),
241 .funcmask = BIT(4),
251 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
252 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
253 BIT(17) | BIT(18),
256 .mask = BIT(31),
259 .mask = BIT(16) | BIT(17),
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/drivers/tty/serial/
Dsirfsoc_uart.h35 #define SIRFUART_DATA_BIT_LEN_5 BIT(0)
40 #define SIRFUART_STOP_BIT_LEN_2 BIT(2)
41 #define SIRFUART_PARITY_EN BIT(3)
42 #define SIRFUART_EVEN_BIT BIT(4)
45 #define SIRFUART_STICK_BIT_EVEN BIT(3)
49 #define SIRFUART_SET_BREAK BIT(6)
50 #define SIRFUART_LOOP_BACK BIT(7)
52 #define SIRFUART_DUMMY_READ BIT(16)
60 #define SIRFUART_AFC_RX_EN BIT(8)
61 #define SIRFUART_AFC_TX_EN BIT(9)
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/drivers/net/ethernet/sgi/
Dmeth.h117 #define SGI_MAC_RESET BIT(0) /* 0: MAC110 active in run mode, 1: Global reset signal to MAC110 cor…
118 #define METH_PHY_FDX BIT(1) /* 0: Disable full duplex, 1: Enable full duplex */
119 #define METH_PHY_LOOP BIT(2) /* 0: Normal operation, follows 10/100mbit and M10T/MII select, 1: loo…
121 #define METH_100MBIT BIT(3) /* 0: 10meg mode, 1: 100meg mode */
122 #define METH_PHY_MII BIT(4) /* 0: MII selected, 1: SIA selected */
132 #define METH_PHY_LINK_FAIL BIT(7) /* 0: Link failure detection disabled, 1: Hardware scans for link…
155 #define METH_DMA_TX_EN BIT(1) /* enable TX DMA */
156 #define METH_DMA_TX_INT_EN BIT(0) /* enable TX Buffer Empty interrupt */
157 #define METH_DMA_RX_EN BIT(15) /* Enable RX */
158 #define METH_DMA_RX_INT_EN BIT(9) /* Enable interrupt on RX packet */
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/drivers/net/wireless/ti/wl1251/
Devent.h39 RESERVED1_EVENT_ID = BIT(0),
40 RESERVED2_EVENT_ID = BIT(1),
41 MEASUREMENT_START_EVENT_ID = BIT(2),
42 SCAN_COMPLETE_EVENT_ID = BIT(3),
43 CALIBRATION_COMPLETE_EVENT_ID = BIT(4),
44 ROAMING_TRIGGER_LOW_RSSI_EVENT_ID = BIT(5),
45 PS_REPORT_EVENT_ID = BIT(6),
46 SYNCHRONIZATION_TIMEOUT_EVENT_ID = BIT(7),
47 HEALTH_REPORT_EVENT_ID = BIT(8),
48 ACI_DETECTION_EVENT_ID = BIT(9),
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