| /drivers/staging/comedi/drivers/addi-data/ |
| D | hwdrv_apci1500.c | 252 devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER); in i_APCI1500_ConfigDigitalInputEvent()
256 outb(0x00, devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER); in i_APCI1500_ConfigDigitalInputEvent()
379 devpriv->iobase + in i_APCI1500_ConfigDigitalInputEvent()
385 devpriv->iobase + in i_APCI1500_ConfigDigitalInputEvent()
391 devpriv->iobase + in i_APCI1500_ConfigDigitalInputEvent()
394 devpriv->iobase + in i_APCI1500_ConfigDigitalInputEvent()
402 devpriv->iobase + in i_APCI1500_ConfigDigitalInputEvent()
405 devpriv->iobase + in i_APCI1500_ConfigDigitalInputEvent()
412 devpriv->iobase + in i_APCI1500_ConfigDigitalInputEvent()
415 devpriv->iobase + in i_APCI1500_ConfigDigitalInputEvent()
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| D | addi_eeprom.c | 53 static void addi_eeprom_clk_93c76(unsigned long iobase, unsigned int val) in addi_eeprom_clk_93c76() argument
55 outl(val & ~EE93C76_CLK_BIT, iobase); in addi_eeprom_clk_93c76()
58 outl(val | EE93C76_CLK_BIT, iobase); in addi_eeprom_clk_93c76()
62 static unsigned int addi_eeprom_cmd_93c76(unsigned long iobase, in addi_eeprom_cmd_93c76() argument
70 outl(val, iobase); in addi_eeprom_cmd_93c76()
81 outl(val, iobase); in addi_eeprom_cmd_93c76()
84 addi_eeprom_clk_93c76(iobase, val); in addi_eeprom_cmd_93c76()
89 static unsigned short addi_eeprom_readw_93c76(unsigned long iobase, in addi_eeprom_readw_93c76() argument
99 cmd = addi_eeprom_cmd_93c76(iobase, cmd, EE93C76_CMD_LEN); in addi_eeprom_readw_93c76()
103 addi_eeprom_clk_93c76(iobase, cmd); in addi_eeprom_readw_93c76()
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| D | hwdrv_apci3501.c | 32 outl(0x0, dev->iobase + APCI3501_TIMER_CTRL_REG); in i_APCI3501_ConfigTimerCounterWatchdog()
36 outl(0x02, dev->iobase + APCI3501_TIMER_CTRL_REG); in i_APCI3501_ConfigTimerCounterWatchdog()
39 outl(0x0, dev->iobase + APCI3501_TIMER_CTRL_REG); in i_APCI3501_ConfigTimerCounterWatchdog()
42 outl(data[2], dev->iobase + APCI3501_TIMER_TIMEBASE_REG); in i_APCI3501_ConfigTimerCounterWatchdog()
43 outl(data[3], dev->iobase + APCI3501_TIMER_RELOAD_REG); in i_APCI3501_ConfigTimerCounterWatchdog()
46 ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG) | 0xFFF819E0UL; in i_APCI3501_ConfigTimerCounterWatchdog()
47 outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG); in i_APCI3501_ConfigTimerCounterWatchdog()
52 ul_Command1 = inl(dev->iobase + APCI3501_TIMER_CTRL_REG); in i_APCI3501_ConfigTimerCounterWatchdog()
54 outl(ul_Command1, dev->iobase + APCI3501_TIMER_CTRL_REG); in i_APCI3501_ConfigTimerCounterWatchdog()
58 outl(0x02, dev->iobase + APCI3501_TIMER_CTRL_REG); in i_APCI3501_ConfigTimerCounterWatchdog()
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| D | hwdrv_apci035.c | 192 outl(ui_Command, devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12); in i_APCI035_ConfigTimerWatchdog()
194 ui_Command = inl(devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12); in i_APCI035_ConfigTimerWatchdog()
198 outl(data[3], devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 4); in i_APCI035_ConfigTimerWatchdog()
202 outl(data[2], devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 8); in i_APCI035_ConfigTimerWatchdog()
238 outl(ui_Command, devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12); in i_APCI035_ConfigTimerWatchdog()
240 ui_Command = inl(devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12); in i_APCI035_ConfigTimerWatchdog()
251 outl(ui_Command, devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12); in i_APCI035_ConfigTimerWatchdog()
253 ui_Command = inl(devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12); in i_APCI035_ConfigTimerWatchdog()
264 outl(ui_Command, devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12); in i_APCI035_ConfigTimerWatchdog()
266 ui_Command = inl(devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12); in i_APCI035_ConfigTimerWatchdog()
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| D | hwdrv_apci3120.c | 334 outw(devpriv->us_OutputRegister, dev->iobase + APCI3120_WR_ADDRESS); in i_APCI3120_SetupChannelList()
348 outw(us_TmpValue, dev->iobase + APCI3120_SEQ_RAM_ADDRESS); in i_APCI3120_SetupChannelList()
399 (unsigned short) inw(devpriv->iobase + APCI3120_RD_STATUS); in i_APCI3120_InsnReadAnalogInput()
419 inw(devpriv->iobase + APCI3120_RESET_FIFO); in i_APCI3120_InsnReadAnalogInput()
435 devpriv->iobase + APCI3120_TIMER_CRT1); in i_APCI3120_InsnReadAnalogInput()
450 inw(devpriv->iobase); in i_APCI3120_InsnReadAnalogInput()
460 devpriv->iobase + APCI3120_WRITE_MODE_SELECT); in i_APCI3120_InsnReadAnalogInput()
468 devpriv->iobase + APCI3120_WR_ADDRESS); in i_APCI3120_InsnReadAnalogInput()
474 outb(b_Tmp, devpriv->iobase + APCI3120_TIMER_CRT0); in i_APCI3120_InsnReadAnalogInput()
478 devpriv->iobase + APCI3120_TIMER_VALUE); in i_APCI3120_InsnReadAnalogInput()
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| D | hwdrv_apci3200.c | 661 while (((inl(devpriv->iobase + s_BoardInfos[dev->minor].i_Offset + in i_APCI3200_Read1AnalogInputChannel()
670 devpriv->iobase + s_BoardInfos[dev->minor].i_Offset + 0x4); in i_APCI3200_Read1AnalogInputChannel()
677 while (((inl(devpriv->iobase + s_BoardInfos[dev->minor].i_Offset + in i_APCI3200_Read1AnalogInputChannel()
682 devpriv->iobase + s_BoardInfos[dev->minor].i_Offset + 36); in i_APCI3200_Read1AnalogInputChannel()
688 while (((inl(devpriv->iobase + s_BoardInfos[dev->minor].i_Offset + in i_APCI3200_Read1AnalogInputChannel()
693 devpriv->iobase + s_BoardInfos[dev->minor].i_Offset + 32); in i_APCI3200_Read1AnalogInputChannel()
717 while (((inl(devpriv->iobase + s_BoardInfos[dev->minor].i_Offset + in i_APCI3200_Read1AnalogInputChannel()
722 devpriv->iobase + s_BoardInfos[dev->minor].i_Offset + 8); in i_APCI3200_Read1AnalogInputChannel()
735 ui_EOC = inl(devpriv->iobase + in i_APCI3200_Read1AnalogInputChannel()
746 inl(devpriv->iobase + in i_APCI3200_Read1AnalogInputChannel()
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| /drivers/net/irda/ |
| D | via-ircc.c | 84 int iobase);
93 static int via_ircc_read_dongle_id(int iobase);
99 static void via_ircc_change_dongle_speed(int iobase, int speed,
101 static int RxTimerHandler(struct via_ircc_cb *self, int iobase);
103 static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase);
104 static int upload_rxdata(struct via_ircc_cb *self, int iobase);
427 int iobase; in via_remove_one() local
431 iobase = self->io.fir_base; in via_remove_one()
433 ResetChip(iobase, 5); //hardware reset. in via_remove_one()
463 int iobase = self->io.fir_base; in via_hw_init() local
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| D | w83977af_ir.c | 90 static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
93 static int w83977af_probe(int iobase, int irq, int dma);
98 static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
99 static void w83977af_dma_write(struct w83977af_ir *self, int iobase);
157 static int w83977af_open(int i, unsigned int iobase, unsigned int irq, in w83977af_open() argument
167 if (!request_region(iobase, CHIP_IO_EXTENT, driver_name)) { in w83977af_open()
169 __func__ , iobase); in w83977af_open()
173 if (w83977af_probe(iobase, irq, dma) == -1) { in w83977af_open()
193 self->io.fir_base = iobase; in w83977af_open()
261 release_region(iobase, CHIP_IO_EXTENT); in w83977af_open()
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| D | via-ircc.h | 286 static void SetMaxRxPacketSize(__u16 iobase, __u16 size) in SetMaxRxPacketSize() argument
292 WriteReg(iobase, I_CF_L_2, low); in SetMaxRxPacketSize()
293 WriteReg(iobase, I_CF_H_2, high); in SetMaxRxPacketSize()
301 static void SetFIFO(__u16 iobase, __u16 value) in SetFIFO() argument
305 WriteRegBit(iobase, 0x11, 0, 0); in SetFIFO()
306 WriteRegBit(iobase, 0x11, 7, 1); in SetFIFO()
309 WriteRegBit(iobase, 0x11, 0, 0); in SetFIFO()
310 WriteRegBit(iobase, 0x11, 7, 0); in SetFIFO()
313 WriteRegBit(iobase, 0x11, 0, 1); in SetFIFO()
314 WriteRegBit(iobase, 0x11, 7, 0); in SetFIFO()
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| D | ali-ircc.c | 120 static int ali_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
138 static void SIR2FIR(int iobase);
139 static void FIR2SIR(int iobase);
422 int iobase; in ali_ircc_close() local
428 iobase = self->io.fir_base; in ali_ircc_close()
559 int iobase = info->fir_base; in ali_ircc_setup() local
569 SIR2FIR(iobase); in ali_ircc_setup()
572 outb(0x40, iobase+FIR_MCR); // benjamin 2000/11/30 11:45AM in ali_ircc_setup()
575 switch_bank(iobase, BANK3); in ali_ircc_setup()
576 version = inb(iobase+FIR_ID_VR); in ali_ircc_setup()
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| D | nsc-ircc.c | 176 static int nsc_ircc_dma_receive_complete(struct nsc_ircc_cb *self, int iobase);
181 static int nsc_ircc_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
182 static void nsc_ircc_dma_xmit(struct nsc_ircc_cb *self, int iobase);
185 static int nsc_ircc_read_dongle_id (int iobase);
186 static void nsc_ircc_init_dongle_interface (int iobase, int dongle_id);
517 int iobase; in nsc_ircc_close() local
523 iobase = self->io.fir_base; in nsc_ircc_close()
985 int iobase = info->fir_base; in nsc_ircc_setup() local
988 switch_bank(iobase, BANK3); in nsc_ircc_setup()
989 version = inb(iobase+MID); in nsc_ircc_setup()
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| D | smsc-ircc2.c | 212 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
362 static inline void register_bank(int iobase, int bank) in register_bank() argument
364 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)), in register_bank()
365 iobase + IRCC_MASTER); in register_bank()
752 int iobase = self->io.fir_base; in smsc_ircc_init_chip() local
754 register_bank(iobase, 0); in smsc_ircc_init_chip()
755 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER); in smsc_ircc_init_chip()
756 outb(0x00, iobase + IRCC_MASTER); in smsc_ircc_init_chip()
758 register_bank(iobase, 1); in smsc_ircc_init_chip()
759 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A), in smsc_ircc_init_chip()
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| /drivers/staging/comedi/drivers/ |
| D | ni_atmio16d.c | 167 outw(0xFFC2, dev->iobase + AM9513A_COM_REG); in reset_counters()
168 outw(0xFF02, dev->iobase + AM9513A_COM_REG); in reset_counters()
169 outw(0x4, dev->iobase + AM9513A_DATA_REG); in reset_counters()
170 outw(0xFF0A, dev->iobase + AM9513A_COM_REG); in reset_counters()
171 outw(0x3, dev->iobase + AM9513A_DATA_REG); in reset_counters()
172 outw(0xFF42, dev->iobase + AM9513A_COM_REG); in reset_counters()
173 outw(0xFF42, dev->iobase + AM9513A_COM_REG); in reset_counters()
175 outw(0xFFC4, dev->iobase + AM9513A_COM_REG); in reset_counters()
176 outw(0xFF03, dev->iobase + AM9513A_COM_REG); in reset_counters()
177 outw(0x4, dev->iobase + AM9513A_DATA_REG); in reset_counters()
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| D | das6402.c | 112 if (!(inb(dev->iobase + 8) & 0x01)) in das6402_ai_fifo_dregs()
114 comedi_buf_put(s->async, inw(dev->iobase)); in das6402_ai_fifo_dregs()
125 outb_p(p, dev->iobase + 15); in das6402_setcounter()
128 outb_p(p, dev->iobase + 12); in das6402_setcounter()
130 outb_p(p, dev->iobase + 12); in das6402_setcounter()
134 outb_p(p, dev->iobase + 15); in das6402_setcounter()
137 outb_p(p, dev->iobase + 13); in das6402_setcounter()
139 outb_p(p, dev->iobase + 13); in das6402_setcounter()
143 outb_p(p, dev->iobase + 15); in das6402_setcounter()
146 outb_p(p, dev->iobase + 14); in das6402_setcounter()
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| D | dmm32at.c | 192 outb(DMM32AT_FIFORESET, dev->iobase + DMM32AT_FIFOCNTRL); in dmm32at_ai_rinsn()
195 outb(chan, dev->iobase + DMM32AT_AILOW); in dmm32at_ai_rinsn()
196 outb(chan, dev->iobase + DMM32AT_AIHIGH); in dmm32at_ai_rinsn()
198 outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AICONF); in dmm32at_ai_rinsn()
202 status = inb(dev->iobase + DMM32AT_AIRBACK); in dmm32at_ai_rinsn()
214 outb(0xff, dev->iobase + DMM32AT_CONV); in dmm32at_ai_rinsn()
217 status = inb(dev->iobase + DMM32AT_AISTAT); in dmm32at_ai_rinsn()
227 lsb = inb(dev->iobase + DMM32AT_AILSB); in dmm32at_ai_rinsn()
228 msb = inb(dev->iobase + DMM32AT_AIMSB); in dmm32at_ai_rinsn()
396 outb(0, dev->iobase + DMM32AT_CNTRDIO); in dmm32at_setaitimer()
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| D | addi_apci_3501.c | 100 status = inl(dev->iobase + APCI3501_AO_CTRL_STATUS_REG); in apci3501_wait_for_dac()
124 outl(0, dev->iobase + APCI3501_AO_CTRL_STATUS_REG); in apci3501_ao_insn_write()
128 dev->iobase + APCI3501_AO_CTRL_STATUS_REG); in apci3501_ao_insn_write()
147 dev->iobase + APCI3501_AO_DATA_REG); in apci3501_ao_insn_write()
160 data[1] = inl(dev->iobase + APCI3501_DI_REG) & 0x3; in apci3501_di_insn_bits()
173 s->state = inl(dev->iobase + APCI3501_DO_REG); in apci3501_do_insn_bits()
178 outl(s->state, dev->iobase + APCI3501_DO_REG); in apci3501_do_insn_bits()
186 static void apci3501_eeprom_wait(unsigned long iobase) in apci3501_eeprom_wait() argument
191 val = inb(iobase + AMCC_OP_REG_MCSR_NVCMD); in apci3501_eeprom_wait()
195 static unsigned short apci3501_eeprom_readw(unsigned long iobase, in apci3501_eeprom_readw() argument
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| D | 8255.c | 103 unsigned long iobase; member
107 static int subdev_8255_io(int dir, int port, int data, unsigned long iobase) in subdev_8255_io() argument
110 outb(data, iobase + port); in subdev_8255_io()
113 return inb(iobase + port); in subdev_8255_io()
121 unsigned long iobase = spriv->iobase; in subdev_8255_interrupt() local
124 d = spriv->io(0, _8255_DATA, 0, iobase); in subdev_8255_interrupt()
125 d |= (spriv->io(0, _8255_DATA + 1, 0, iobase) << 8); in subdev_8255_interrupt()
139 unsigned long iobase = spriv->iobase; in subdev_8255_insn() local
153 spriv->io(1, _8255_DATA, v & 0xff, iobase); in subdev_8255_insn()
155 spriv->io(1, _8255_DATA + 1, (v >> 8) & 0xff, iobase); in subdev_8255_insn()
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| D | adv_pci_dio.c | 427 data[1] |= inb(dev->iobase + d->addr + i) << (8 * i); in pci_dio_insn_bits_di_b()
445 data[1] |= inw(dev->iobase + d->addr + 2 * i) << (16 * i); in pci_dio_insn_bits_di_w()
465 dev->iobase + d->addr + i); in pci_dio_insn_bits_do_b()
487 dev->iobase + d->addr + 2 * i); in pci_dio_insn_bits_do_w()
509 data[0] = i8254_read(dev->iobase + d->addr + (SIZE_8254 * chip), in pci_8254_insn_read()
530 i8254_write(dev->iobase + d->addr + (SIZE_8254 * chip), in pci_8254_insn_write()
545 unsigned long iobase; in pci_8254_insn_config() local
552 iobase = dev->iobase + d->addr + (SIZE_8254 * chip); in pci_8254_insn_config()
556 ret = i8254_set_mode(iobase, 0, chipchan, data[1]); in pci_8254_insn_config()
561 data[1] = i8254_status(iobase, 0, chipchan); in pci_8254_insn_config()
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| D | pcl818.c | 332 outb(0, dev->iobase + PCL818_CONTROL); in pcl818_ai_insn_read()
335 outb(muxonechan[CR_CHAN(insn->chanspec)], dev->iobase + PCL818_MUX); in pcl818_ai_insn_read()
338 outb(CR_RANGE(insn->chanspec), dev->iobase + PCL818_RANGE); in pcl818_ai_insn_read()
343 outb(0, dev->iobase + PCL818_CLRINT); in pcl818_ai_insn_read()
346 outb(0, dev->iobase + PCL818_AD_LO); in pcl818_ai_insn_read()
350 if (inb(dev->iobase + PCL818_STATUS) & 0x10) in pcl818_ai_insn_read()
356 outb(0, dev->iobase + PCL818_CLRINT); in pcl818_ai_insn_read()
360 data[n] = ((inb(dev->iobase + PCL818_AD_HI) << 4) | in pcl818_ai_insn_read()
361 (inb(dev->iobase + PCL818_AD_LO) >> 4)); in pcl818_ai_insn_read()
396 outb((data[n] & 0x000f) << 4, dev->iobase + in pcl818_ao_insn_write()
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| D | adv_pci1710.c | 404 outw(chanprog, dev->iobase + PCI171x_MUX); /* select channel */ in setup_channel_list()
408 outw(range, dev->iobase + PCI171x_RANGE); /* select gain */ in setup_channel_list()
424 outw(devpriv->ai_et_MuxVal, dev->iobase + PCI171x_MUX); in setup_channel_list()
443 outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL); in pci171x_insn_read_ai()
444 outb(0, dev->iobase + PCI171x_CLRFIFO); in pci171x_insn_read_ai()
445 outb(0, dev->iobase + PCI171x_CLRINT); in pci171x_insn_read_ai()
450 outw(0, dev->iobase + PCI171x_SOFTTRG); /* start conversion */ in pci171x_insn_read_ai()
454 if (!(inw(dev->iobase + PCI171x_STATUS) & Status_FE)) in pci171x_insn_read_ai()
458 outb(0, dev->iobase + PCI171x_CLRFIFO); in pci171x_insn_read_ai()
459 outb(0, dev->iobase + PCI171x_CLRINT); in pci171x_insn_read_ai()
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| D | ni_daq_700.c | 87 outb(s->state & 0xff, dev->iobase + DIO_W); in daq700_dio_insn_bits()
91 data[1] |= inb(dev->iobase + DIO_R) << 8; in daq700_dio_insn_bits()
129 outb(chan | 0x80, dev->iobase + CMD_R1); in daq700_ai_rinsn()
134 outb(0x00, dev->iobase + CMD_R2); /* enable ADC conversions */ in daq700_ai_rinsn()
135 outb(0x30, dev->iobase + CMO_R); /* mode 0 out0 L, from H */ in daq700_ai_rinsn()
137 outb(0x32, dev->iobase + CMO_R); in daq700_ai_rinsn()
140 status = inb(dev->iobase + STA_R2); in daq700_ai_rinsn()
146 status = inb(dev->iobase + STA_R1); in daq700_ai_rinsn()
163 d = inw(dev->iobase + ADFIFO_R); in daq700_ai_rinsn()
187 unsigned long iobase = dev->iobase; in daq700_ai_config() local
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| /drivers/bluetooth/ |
| D | bt3c_cs.c | 116 static inline void bt3c_address(unsigned int iobase, unsigned short addr) in bt3c_address() argument
118 outb(addr & 0xff, iobase + ADDR_L); in bt3c_address()
119 outb((addr >> 8) & 0xff, iobase + ADDR_H); in bt3c_address()
123 static inline void bt3c_put(unsigned int iobase, unsigned short value) in bt3c_put() argument
125 outb(value & 0xff, iobase + DATA_L); in bt3c_put()
126 outb((value >> 8) & 0xff, iobase + DATA_H); in bt3c_put()
130 static inline void bt3c_io_write(unsigned int iobase, unsigned short addr, unsigned short value) in bt3c_io_write() argument
132 bt3c_address(iobase, addr); in bt3c_io_write()
133 bt3c_put(iobase, value); in bt3c_io_write()
137 static inline unsigned short bt3c_get(unsigned int iobase) in bt3c_get() argument
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| D | bluecard_cs.c | 161 unsigned int iobase = info->p_dev->resource[0]->start; in bluecard_activity_led_timeout() local
168 outb(0x08 | 0x20, iobase + 0x30); in bluecard_activity_led_timeout()
171 outb(0x00, iobase + 0x30); in bluecard_activity_led_timeout()
178 unsigned int iobase = info->p_dev->resource[0]->start; in bluecard_enable_activity_led() local
185 outb(0x10 | 0x40, iobase + 0x30); in bluecard_enable_activity_led()
191 outb(0x08 | 0x20, iobase + 0x30); in bluecard_enable_activity_led()
203 static int bluecard_write(unsigned int iobase, unsigned int offset, __u8 *buf, int len) in bluecard_write() argument
209 outb_p(actual, iobase + offset); in bluecard_write()
212 outb_p(buf[i], iobase + offset + i + 1); in bluecard_write()
234 unsigned int iobase = info->p_dev->resource[0]->start; in bluecard_write_wakeup() local
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| /drivers/net/hamradio/ |
| D | baycom_ser_fdx.c | 106 #define RBR(iobase) (iobase+0) argument
107 #define THR(iobase) (iobase+0) argument
108 #define IER(iobase) (iobase+1) argument
109 #define IIR(iobase) (iobase+2) argument
110 #define FCR(iobase) (iobase+2) argument
111 #define LCR(iobase) (iobase+3) argument
112 #define MCR(iobase) (iobase+4) argument
113 #define LSR(iobase) (iobase+5) argument
114 #define MSR(iobase) (iobase+6) argument
115 #define SCR(iobase) (iobase+7) argument
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| D | baycom_ser_hdx.c | 94 #define RBR(iobase) (iobase+0) argument
95 #define THR(iobase) (iobase+0) argument
96 #define IER(iobase) (iobase+1) argument
97 #define IIR(iobase) (iobase+2) argument
98 #define FCR(iobase) (iobase+2) argument
99 #define LCR(iobase) (iobase+3) argument
100 #define MCR(iobase) (iobase+4) argument
101 #define LSR(iobase) (iobase+5) argument
102 #define MSR(iobase) (iobase+6) argument
103 #define SCR(iobase) (iobase+7) argument
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