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Searched refs:gpu_addr (Results 1 – 25 of 119) sorted by relevance

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/drivers/gpu/drm/radeon/
Dr600_dma.c144 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
146 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_dma_resume()
151 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); in r600_dma_resume()
237 u64 gpu_addr; in r600_dma_ring_test() local
244 gpu_addr = rdev->wb.gpu_addr + index; in r600_dma_ring_test()
255 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in r600_dma_ring_test()
256 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in r600_dma_ring_test()
291 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_dma_fence_ring_emit()
318 u64 addr = semaphore->gpu_addr; in r600_dma_semaphore_ring_emit()
344 u64 gpu_addr; in r600_dma_ib_test() local
[all …]
Dcik_sdma.c155 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_ib_execute()
156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
204 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_sdma_fence_ring_emit()
233 u64 addr = semaphore->gpu_addr; in cik_sdma_semaphore_ring_emit()
401 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
403 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); in cik_sdma_gfx_resume()
408 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); in cik_sdma_gfx_resume()
409 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); in cik_sdma_gfx_resume()
652 u64 gpu_addr; in cik_sdma_ring_test() local
659 gpu_addr = rdev->wb.gpu_addr + index; in cik_sdma_ring_test()
[all …]
Duvd_v4_2.c47 addr = (rdev->uvd.gpu_addr + 0x200) >> 3; in uvd_v4_2_resume()
49 addr = rdev->uvd.gpu_addr >> 3; in uvd_v4_2_resume()
67 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_resume()
71 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_resume()
Duvd_v2_2.c43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v2_2_fence_emit()
77 uint64_t addr = semaphore->gpu_addr; in uvd_v2_2_semaphore_emit()
113 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume()
130 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume()
134 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
Duvd_v1_0.c85 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; in uvd_v1_0_fence_emit()
121 addr = (rdev->uvd.gpu_addr >> 3) + 16; in uvd_v1_0_resume()
138 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v1_0_resume()
142 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v1_0_resume()
364 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | in uvd_v1_0_start()
374 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); in uvd_v1_0_start()
487 radeon_ring_write(ring, ib->gpu_addr); in uvd_v1_0_ib_execute()
Dradeon_semaphore.c51 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo); in radeon_semaphore_create()
69 ring->last_semaphore_signal_addr = semaphore->gpu_addr; in radeon_semaphore_emit_signal()
86 ring->last_semaphore_wait_addr = semaphore->gpu_addr; in radeon_semaphore_emit_wait()
Dvce_v1_0.c218 uint64_t addr = rdev->vce.gpu_addr; in vce_v1_0_resume()
300 WREG32(VCE_RB_BASE_LO, ring->gpu_addr); in vce_v1_0_start()
301 WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
307 WREG32(VCE_RB_BASE_LO2, ring->gpu_addr); in vce_v1_0_start()
308 WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v1_0_start()
Dradeon_trace.h177 __field(uint64_t, gpu_addr)
183 __entry->gpu_addr = sem->gpu_addr;
187 __entry->waiters, __entry->gpu_addr)
Devergreen_dma.c45 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
89 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in evergreen_dma_ring_ib_execute()
90 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in evergreen_dma_ring_ib_execute()
/drivers/gpu/drm/amd/amdgpu/
Dvce_v4_0.c154 uint64_t addr = table->gpu_addr; in vce_v4_0_mmsch_start()
232 lower_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start()
234 upper_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start()
254 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
256 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
258 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
325 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), ring->gpu_addr); in vce_v4_0_start()
326 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); in vce_v4_0_start()
333 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO2), ring->gpu_addr); in vce_v4_0_start()
334 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI2), upper_32_bits(ring->gpu_addr)); in vce_v4_0_start()
[all …]
Damdgpu_virt.c242 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) in amdgpu_virt_alloc_mm_table()
248 &adev->virt.mm_table.gpu_addr, in amdgpu_virt_alloc_mm_table()
257 adev->virt.mm_table.gpu_addr, in amdgpu_virt_alloc_mm_table()
269 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) in amdgpu_virt_free_mm_table()
273 &adev->virt.mm_table.gpu_addr, in amdgpu_virt_free_mm_table()
275 adev->virt.mm_table.gpu_addr = 0; in amdgpu_virt_free_mm_table()
Duvd_v7_0.c223 dummy = ib->gpu_addr + 1024; in uvd_v7_0_enc_get_create_msg()
286 dummy = ib->gpu_addr + 1024; in uvd_v7_0_enc_get_destroy_msg()
636 lower_32_bits(adev->uvd.gpu_addr)); in uvd_v7_0_mc_resume()
638 upper_32_bits(adev->uvd.gpu_addr)); in uvd_v7_0_mc_resume()
647 lower_32_bits(adev->uvd.gpu_addr + offset)); in uvd_v7_0_mc_resume()
649 upper_32_bits(adev->uvd.gpu_addr + offset)); in uvd_v7_0_mc_resume()
654 lower_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); in uvd_v7_0_mc_resume()
656 upper_32_bits(adev->uvd.gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); in uvd_v7_0_mc_resume()
675 uint64_t addr = table->gpu_addr; in uvd_v7_0_mmsch_start()
766 lower_32_bits(adev->uvd.gpu_addr)); in uvd_v7_0_sriov_start()
[all …]
Dsi_dma.c72 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); in si_dma_ring_emit_ib()
73 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
167 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); in si_dma_start()
174 WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in si_dma_start()
222 u64 gpu_addr; in si_dma_ring_test_ring() local
230 gpu_addr = adev->wb.gpu_addr + (index * 4); in si_dma_ring_test_ring()
242 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in si_dma_ring_test_ring()
243 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in si_dma_ring_test_ring()
281 u64 gpu_addr; in si_dma_ring_test_ib() local
290 gpu_addr = adev->wb.gpu_addr + (index * 4); in si_dma_ring_test_ib()
[all …]
Damdgpu_object.h203 u64 *gpu_addr, void **cpu_addr);
207 u64 *gpu_addr, void **cpu_addr);
208 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
215 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
218 u64 *gpu_addr);
259 return sa_bo->manager->gpu_addr + sa_bo->soffset; in amdgpu_sa_bo_gpu_addr()
Dvcn_v1_0.c272 lower_32_bits(adev->vcn.gpu_addr)); in vcn_v1_0_mc_resume()
274 upper_32_bits(adev->vcn.gpu_addr)); in vcn_v1_0_mc_resume()
283 lower_32_bits(adev->vcn.gpu_addr + offset)); in vcn_v1_0_mc_resume()
285 upper_32_bits(adev->vcn.gpu_addr + offset)); in vcn_v1_0_mc_resume()
290 lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE)); in vcn_v1_0_mc_resume()
292 upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE)); in vcn_v1_0_mc_resume()
640 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start()
644 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start()
646 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start()
661 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v1_0_start()
[all …]
Damdgpu_object.c196 u64 *gpu_addr, void **cpu_addr) in amdgpu_bo_create_reserved() argument
220 r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr); in amdgpu_bo_create_reserved()
264 u64 *gpu_addr, void **cpu_addr) in amdgpu_bo_create_kernel() argument
269 gpu_addr, cpu_addr); in amdgpu_bo_create_kernel()
286 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, in amdgpu_bo_free_kernel() argument
301 if (gpu_addr) in amdgpu_bo_free_kernel()
302 *gpu_addr = 0; in amdgpu_bo_free_kernel()
673 u64 *gpu_addr) in amdgpu_bo_pin_restricted() argument
700 if (gpu_addr) in amdgpu_bo_pin_restricted()
701 *gpu_addr = amdgpu_bo_gpu_offset(bo); in amdgpu_bo_pin_restricted()
[all …]
Dvce_v3_0.c283 WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr); in vce_v3_0_start()
284 WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
290 WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr); in vce_v3_0_start()
291 WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
297 WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr); in vce_v3_0_start()
298 WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr)); in vce_v3_0_start()
543 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
544 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
545 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
547 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); in vce_v3_0_mc_resume()
[all …]
Damdgpu_amdkfd.c170 void **mem_obj, uint64_t *gpu_addr, in alloc_gtt_mem() argument
178 BUG_ON(gpu_addr == NULL); in alloc_gtt_mem()
202 &(*mem)->gpu_addr); in alloc_gtt_mem()
207 *gpu_addr = (*mem)->gpu_addr; in alloc_gtt_mem()
Dcik_sdma.c232 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_emit_ib()
233 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
483 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
485 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); in cik_sdma_gfx_resume()
489 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in cik_sdma_gfx_resume()
490 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); in cik_sdma_gfx_resume()
627 u64 gpu_addr; in cik_sdma_ring_test_ring() local
635 gpu_addr = adev->wb.gpu_addr + (index * 4); in cik_sdma_ring_test_ring()
646 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
647 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
[all …]
Dsdma_v2_4.c259 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
260 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
459 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in sdma_v2_4_gfx_resume()
461 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v2_4_gfx_resume()
465 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in sdma_v2_4_gfx_resume()
466 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); in sdma_v2_4_gfx_resume()
611 u64 gpu_addr; in sdma_v2_4_ring_test_ring() local
619 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v2_4_ring_test_ring()
632 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
633 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
[all …]
Damdgpu_fence.c152 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, in amdgpu_fence_emit()
339 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4); in amdgpu_fence_driver_start_ring()
344 ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index; in amdgpu_fence_driver_start_ring()
355 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr); in amdgpu_fence_driver_start_ring()
380 ring->fence_drv.gpu_addr = 0; in amdgpu_fence_driver_init_ring()
Dsdma_v4_0.c356 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_0_ring_emit_ib()
357 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v4_0_ring_emit_ib()
611 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in sdma_v4_0_gfx_resume()
613 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v4_0_gfx_resume()
617 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); in sdma_v4_0_gfx_resume()
618 WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); in sdma_v4_0_gfx_resume()
666 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in sdma_v4_0_gfx_resume()
887 u64 gpu_addr; in sdma_v4_0_ring_test_ring() local
895 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v4_0_ring_test_ring()
908 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v4_0_ring_test_ring()
[all …]
Dsdma_v3_0.c425 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
426 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v3_0_ring_emit_ib()
690 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in sdma_v3_0_gfx_resume()
692 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v3_0_gfx_resume()
696 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); in sdma_v3_0_gfx_resume()
697 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); in sdma_v3_0_gfx_resume()
855 u64 gpu_addr; in sdma_v3_0_ring_test_ring() local
863 gpu_addr = adev->wb.gpu_addr + (index * 4); in sdma_v3_0_ring_test_ring()
876 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v3_0_ring_test_ring()
877 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v3_0_ring_test_ring()
[all …]
/drivers/gpu/drm/mgag200/
Dmgag200_cursor.c53 u64 gpu_addr; in mga_crtc_cursor_set() local
218 gpu_addr = mdev->cursor.pixels_1_gpu_addr; in mga_crtc_cursor_set()
220 gpu_addr = mdev->cursor.pixels_2_gpu_addr; in mga_crtc_cursor_set()
221 WREG_DAC(MGA1064_CURSOR_BASE_ADR_LOW, (u8)((gpu_addr>>10) & 0xff)); in mga_crtc_cursor_set()
222 WREG_DAC(MGA1064_CURSOR_BASE_ADR_HI, (u8)((gpu_addr>>18) & 0x3f)); in mga_crtc_cursor_set()
/drivers/gpu/drm/qxl/
Dqxl_object.c224 static int __qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr) in __qxl_bo_pin() argument
231 if (gpu_addr) in __qxl_bo_pin()
232 *gpu_addr = qxl_bo_gpu_offset(bo); in __qxl_bo_pin()
239 if (gpu_addr != NULL) in __qxl_bo_pin()
240 *gpu_addr = qxl_bo_gpu_offset(bo); in __qxl_bo_pin()
273 int qxl_bo_pin(struct qxl_bo *bo, u32 domain, u64 *gpu_addr) in qxl_bo_pin() argument

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