Searched refs:BIT (Results 1 – 25 of 2333) sorted by relevance
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18 #define SYS_ISO_MD2PP BIT(0)19 #define SYS_ISO_ANALOG_IPS BIT(5)20 #define SYS_ISO_DIOR BIT(9)21 #define SYS_ISO_PWC_EV25V BIT(14)22 #define SYS_ISO_PWC_EV12V BIT(15)25 #define SYS_FUNC_BBRSTB BIT(0)26 #define SYS_FUNC_BB_GLB_RSTN BIT(1)27 #define SYS_FUNC_USBA BIT(2)28 #define SYS_FUNC_UPLL BIT(3)29 #define SYS_FUNC_USBD BIT(4)[all …]
340 #define RXERR_RPT_RST BIT(27)443 #define CmdEEPROM_En BIT(5)445 #define CmdEERPOMSEL BIT(4)446 #define Cmd9346CR_9356SEL BIT(4)450 #define GPIOSEL_ENBT BIT(5)463 #define HSIMR_GPIO12_0_INT_EN BIT(0)464 #define HSIMR_SPS_OCP_INT_EN BIT(5)465 #define HSIMR_RON_INT_EN BIT(6)466 #define HSIMR_PDN_INT_EN BIT(7)467 #define HSIMR_GPIO9_INT_EN BIT(25)[all …]
6 #define DE_STATE1_DE_ABORT BIT(0)9 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)10 #define DE_STATE2_DE_STATUS_BUSY BIT(2)11 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)19 #define SYSTEM_CTRL_PCI_BURST BIT(29)20 #define SYSTEM_CTRL_PCI_MASTER BIT(25)21 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)22 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)23 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)24 #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21)[all …]
33 #define NISTC_INTA_ACK_G0_GATE BIT(15)34 #define NISTC_INTA_ACK_G0_TC BIT(14)35 #define NISTC_INTA_ACK_AI_ERR BIT(13)36 #define NISTC_INTA_ACK_AI_STOP BIT(12)37 #define NISTC_INTA_ACK_AI_START BIT(11)38 #define NISTC_INTA_ACK_AI_START2 BIT(10)39 #define NISTC_INTA_ACK_AI_START1 BIT(9)40 #define NISTC_INTA_ACK_AI_SC_TC BIT(8)41 #define NISTC_INTA_ACK_AI_SC_TC_ERR BIT(7)42 #define NISTC_INTA_ACK_G0_TC_ERR BIT(6)[all …]
62 #define PLX_LASRR_IO BIT(0) /* Map to: 1=I/O, 0=Mem */63 #define PLX_LASRR_MLOC_ANY32 (BIT(1) * 0) /* Locate anywhere in 32 bit */64 #define PLX_LASRR_MLOC_LT1MB (BIT(1) * 1) /* Locate in 1st meg */65 #define PLX_LASRR_MLOC_ANY64 (BIT(1) * 2) /* Locate anywhere in 64 bit */67 #define PLX_LASRR_PREFETCH BIT(3) /* Memory is prefetchable */78 #define PLX_LASBA_EN BIT(0) /* Enable slave decode */90 #define PLX_MARBR_LT(x) (BIT(0) * ((x) & 0xff))94 #define PLX_MARBR_PT(x) (BIT(8) * ((x) & 0xff))98 #define PLX_MARBR_LTEN BIT(16)100 #define PLX_MARBR_PTEN BIT(17)[all …]
35 #define SP_VIDEO_RST BIT(4)36 #define SP_HDCP_MAN_RST BIT(2)37 #define SP_TMDS_RST BIT(1)38 #define SP_SW_MAN_RST BIT(0)42 #define SP_TMDS_CLOCK_DET BIT(1)43 #define SP_TMDS_DE_DET BIT(0)47 #define SP_HDMI_AUD_LAYOUT BIT(3)48 #define SP_HDMI_DET BIT(0)54 #define SP_AUD_MUTE BIT(1)55 #define SP_VID_MUTE BIT(0)[all …]
92 # define IRQSTATUS_LATCHED_MSG BIT(0)93 # define IRQSTATUS_LATCHED_IO BIT(1)94 # define IRQSTATUS_LATCHED_CD BIT(2)95 # define IRQSTATUS_LATCHED_BUS_FREE BIT(3)96 # define IRQSTATUS_RESELECT_OCCUER BIT(4)97 # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)98 # define IRQSTATUS_SCSIRESET_IRQ BIT(6)99 # define IRQSTATUS_TIMER_IRQ BIT(7)100 # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)101 # define IRQSTATUS_PCI_IRQ BIT(9)[all …]
138 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |139 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |140 BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |141 BIT(17) | BIT(18),144 .mask = BIT(31),152 .funcmask = BIT(4),162 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |163 BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |164 BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |165 BIT(17) | BIT(18),[all …]
134 .mask = BIT(30) | BIT(31),137 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |138 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |139 BIT(16) | BIT(17) | BIT(18) | BIT(19) |140 BIT(20) | BIT(21) | BIT(22) | BIT(31),148 .funcmask = BIT(4),158 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |159 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |160 BIT(16) | BIT(17) | BIT(18) | BIT(19) |161 BIT(20) | BIT(21) | BIT(22) | BIT(31),[all …]
94 #define MAC0_ON BIT(7)95 #define MAC1_ON BIT(0)96 #define MAC0_READY BIT(0)97 #define MAC1_READY BIT(0)443 #define RATE_1M BIT(0)444 #define RATE_2M BIT(1)445 #define RATE_5_5M BIT(2)446 #define RATE_11M BIT(3)448 #define RATE_6M BIT(4)449 #define RATE_9M BIT(5)[all …]
27 #define TW5864_EMU_EN_DDR BIT(0)29 #define TW5864_EMU_EN_ME BIT(1)31 #define TW5864_EMU_EN_SEN BIT(2)33 #define TW5864_EMU_EN_BHOST BIT(3)35 #define TW5864_EMU_EN_LPF BIT(4)37 #define TW5864_EMU_EN_PLBK BIT(5)47 #define TW5864_DSP_FRAME_TYPE_D1 BIT(6)54 #define TW5864_VLC_SLICE_END BIT(0)56 #define TW5864_MAS_SLICE_END BIT(4)58 #define TW5864_START_NSLICE BIT(15)[all …]
327 #define RXDMA_AGG_EN BIT(7)333 #define ISO_MD2PP BIT(0)334 #define ISO_PA2PCIE BIT(3)335 #define ISO_PLL2MD BIT(4)336 #define ISO_PWC_DV2RP BIT(11)337 #define ISO_PWC_RV2RP BIT(12)340 #define FEN_MREGEN BIT(15)341 #define FEN_DCORE BIT(11)342 #define FEN_CPUEN BIT(10)344 #define PAD_HWPD_IDN BIT(22)[all …]
342 #define CMDEEPROM_EN BIT(5)343 #define CMDEEPROM_SEL BIT(4)344 #define CMD9346CR_9356SEL BIT(4)349 #define GPIOSEL_ENBT BIT(5)367 #define RRSR_1M BIT(0)368 #define RRSR_2M BIT(1)369 #define RRSR_5_5M BIT(2)370 #define RRSR_11M BIT(3)371 #define RRSR_6M BIT(4)372 #define RRSR_9M BIT(5)[all …]
63 #define ALX_UE_SVRT_FCPROTERR BIT(13)64 #define ALX_UE_SVRT_DLPROTERR BIT(4)68 #define ALX_EFLD_F_EXIST BIT(10)69 #define ALX_EFLD_E_EXIST BIT(9)70 #define ALX_EFLD_STAT BIT(5)71 #define ALX_EFLD_START BIT(0)75 #define ALX_SLD_STAT BIT(12)76 #define ALX_SLD_START BIT(11)80 #define ALX_PDLL_TRNS1_D3PLLOFF_EN BIT(11)83 #define ALX_PMCTRL_HOTRST_WTEN BIT(31)[all …]
32 #define RDES0_PAYLOAD_CSUM_ERR BIT(0)33 #define RDES0_CRC_ERROR BIT(1)34 #define RDES0_DRIBBLING BIT(2)35 #define RDES0_MII_ERROR BIT(3)36 #define RDES0_RECEIVE_WATCHDOG BIT(4)37 #define RDES0_FRAME_TYPE BIT(5)38 #define RDES0_COLLISION BIT(6)39 #define RDES0_IPC_CSUM_ERROR BIT(7)40 #define RDES0_LAST_DESCRIPTOR BIT(8)41 #define RDES0_FIRST_DESCRIPTOR BIT(9)[all …]
374 #define CMDEEPROM_EN BIT(5)375 #define CMDEEPROM_SEL BIT(4)376 #define CMD9346CR_9356SEL BIT(4)381 #define GPIOSEL_ENBT BIT(5)391 #define HSIMR_GPIO12_0_INT_EN BIT(0)392 #define HSIMR_SPS_OCP_INT_EN BIT(5)393 #define HSIMR_RON_INT_EN BIT(6)394 #define HSIMR_PDN_INT_EN BIT(7)395 #define HSIMR_GPIO9_INT_EN BIT(25)400 #define HSISR_GPIO12_0_INT BIT(0)[all …]
404 #define CMDEEPROM_EN BIT(5)405 #define CMDEEPROM_SEL BIT(4)406 #define CMD9346CR_9356SEL BIT(4)411 #define GPIOSEL_ENBT BIT(5)429 #define RRSR_1M BIT(0)430 #define RRSR_2M BIT(1)431 #define RRSR_5_5M BIT(2)432 #define RRSR_11M BIT(3)433 #define RRSR_6M BIT(4)434 #define RRSR_9M BIT(5)[all …]
78 #define USART_SR_PE BIT(0)79 #define USART_SR_FE BIT(1)80 #define USART_SR_NF BIT(2)81 #define USART_SR_ORE BIT(3)82 #define USART_SR_IDLE BIT(4)83 #define USART_SR_RXNE BIT(5)84 #define USART_SR_TC BIT(6)85 #define USART_SR_TXE BIT(7)86 #define USART_SR_LBD BIT(8)87 #define USART_SR_CTSIF BIT(9)[all …]
360 #define CMDEEPROM_EN BIT(5)361 #define CMDEEPROM_SEL BIT(4)362 #define CMD9346CR_9356SEL BIT(4)367 #define GPIOSEL_ENBT BIT(5)386 #define RRSR_1M BIT(0)387 #define RRSR_2M BIT(1)388 #define RRSR_5_5M BIT(2)389 #define RRSR_11M BIT(3)390 #define RRSR_6M BIT(4)391 #define RRSR_9M BIT(5)[all …]
400 #define CMDEEPROM_EN BIT(5)401 #define CMDEEPROM_SEL BIT(4)402 #define CMD9346CR_9356SEL BIT(4)407 #define GPIOSEL_ENBT BIT(5)415 #define HSIMR_GPIO12_0_INT_EN BIT(0)416 #define HSIMR_SPS_OCP_INT_EN BIT(5)417 #define HSIMR_RON_INT_EN BIT(6)418 #define HSIMR_PDN_INT_EN BIT(7)419 #define HSIMR_GPIO9_INT_EN BIT(25)422 #define HSISR_GPIO12_0_INT BIT(0)[all …]
389 #define CMDEEPROM_EN BIT(5)390 #define CMDEEPROM_SEL BIT(4)391 #define CMD9346CR_9356SEL BIT(4)396 #define GPIOSEL_ENBT BIT(5)404 #define HSIMR_GPIO12_0_INT_EN BIT(0)405 #define HSIMR_SPS_OCP_INT_EN BIT(5)406 #define HSIMR_RON_INT_EN BIT(6)407 #define HSIMR_PDN_INT_EN BIT(7)408 #define HSIMR_GPIO9_INT_EN BIT(25)411 #define HSISR_GPIO12_0_INT BIT(0)[all …]
20 #define LR_SWAP BIT(0)21 #define LFE_CC_SWAP BIT(1)22 #define LSRS_SWAP BIT(2)23 #define RLS_RRS_SWAP BIT(3)24 #define LR_STATUS_SWAP BIT(4)31 #define I2S_UV_V BIT(0)32 #define I2S_UV_U BIT(1)34 #define I2S_UV_CH_EN(x) BIT((x) + 2)35 #define I2S_UV_TMDS_DEBUG BIT(6)36 #define I2S_UV_NORMAL_INFO_INV BIT(7)[all …]
32 #define HCCPARAMS_LEN BIT(17)36 #define DCCPARAMS_DC BIT(7)37 #define DCCPARAMS_HC BIT(8)40 #define TESTMODE_FORCE BIT(0)43 #define USBCMD_RS BIT(0)44 #define USBCMD_RST BIT(1)45 #define USBCMD_SUTW BIT(13)46 #define USBCMD_ATDTW BIT(14)49 #define USBi_UI BIT(0)50 #define USBi_UEI BIT(1)[all …]
26 #define MT_CMB_CTRL_XTAL_RDY BIT(22)27 #define MT_CMB_CTRL_PLL_LD BIT(23)35 #define MT_EFUSE_CTRL_KICK BIT(30)36 #define MT_EFUSE_CTRL_SEL BIT(31)42 #define MT_COEXCFG0_COEX_EN BIT(0)45 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)46 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)47 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)49 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */50 #define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */[all …]
25 #define ISS_HL_SYSCONFIG_SOFTRESET BIT(0)32 #define ISS_HL_IRQ_HS_VS BIT(17)33 #define ISS_HL_IRQ_SIMCOP(i) BIT(12 + (i))34 #define ISS_HL_IRQ_BTE BIT(11)35 #define ISS_HL_IRQ_CBUFF BIT(10)36 #define ISS_HL_IRQ_CCP2(i) BIT((i) > 3 ? 16 : 14 + (i))37 #define ISS_HL_IRQ_CSIB BIT(5)38 #define ISS_HL_IRQ_CSIA BIT(4)39 #define ISS_HL_IRQ_ISP(i) BIT(i)49 #define ISS_CLKCTRL_VPORT2_CLK BIT(30)[all …]