| /drivers/gpu/drm/bridge/analogix/ |
| D | analogix_dp_reg.c | 31 u32 reg; in analogix_dp_enable_video_mute() local
34 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
35 reg |= HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
36 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
38 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
39 reg &= ~HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute()
40 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute()
46 u32 reg; in analogix_dp_stop_video() local
48 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video()
49 reg &= ~VIDEO_EN; in analogix_dp_stop_video()
[all …]
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| /drivers/scsi/qla2xxx/ |
| D | qla_dbg.c | 116 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla27xx_dump_mpi_ram() local
123 WRT_REG_WORD(®->mailbox0, MBC_LOAD_DUMP_MPI_RAM); in qla27xx_dump_mpi_ram()
132 WRT_REG_WORD(®->mailbox1, LSW(addr)); in qla27xx_dump_mpi_ram()
133 WRT_REG_WORD(®->mailbox8, MSW(addr)); in qla27xx_dump_mpi_ram()
135 WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); in qla27xx_dump_mpi_ram()
136 WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); in qla27xx_dump_mpi_ram()
137 WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
138 WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram()
140 WRT_REG_WORD(®->mailbox4, MSW(dwords)); in qla27xx_dump_mpi_ram()
141 WRT_REG_WORD(®->mailbox5, LSW(dwords)); in qla27xx_dump_mpi_ram()
[all …]
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| /drivers/memory/tegra/ |
| D | tegra210.c | 28 .reg = 0x228,
32 .reg = 0x2e8,
42 .reg = 0x228,
46 .reg = 0x2f4,
56 .reg = 0x228,
60 .reg = 0x2e8,
70 .reg = 0x228,
74 .reg = 0x2f4,
84 .reg = 0x228,
88 .reg = 0x2ec,
[all …]
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| D | tegra114.c | 26 .reg = 0x228,
30 .reg = 0x2e8,
40 .reg = 0x228,
44 .reg = 0x2f4,
54 .reg = 0x228,
58 .reg = 0x2e8,
68 .reg = 0x228,
72 .reg = 0x2f4,
82 .reg = 0x228,
86 .reg = 0x2ec,
[all …]
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| D | tegra124.c | 68 .reg = 0x228,
72 .reg = 0x2e8,
82 .reg = 0x228,
86 .reg = 0x2f4,
96 .reg = 0x228,
100 .reg = 0x2e8,
110 .reg = 0x228,
114 .reg = 0x2f4,
124 .reg = 0x228,
128 .reg = 0x2ec,
[all …]
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| D | tegra30.c | 26 .reg = 0x228,
30 .reg = 0x2e8,
40 .reg = 0x228,
44 .reg = 0x2f4,
54 .reg = 0x228,
58 .reg = 0x2e8,
68 .reg = 0x228,
72 .reg = 0x2f4,
82 .reg = 0x228,
86 .reg = 0x2ec,
[all …]
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| /drivers/media/platform/s5p-jpeg/ |
| D | jpeg-hw-s5p.c | 22 unsigned long reg; in s5p_jpeg_reset() local
25 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
27 while (reg != 0) { in s5p_jpeg_reset()
29 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset()
40 unsigned long reg, m; in s5p_jpeg_input_raw_mode() local
48 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
49 reg &= ~S5P_MOD_SEL_MASK; in s5p_jpeg_input_raw_mode()
50 reg |= m; in s5p_jpeg_input_raw_mode()
51 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode()
56 unsigned long reg, m; in s5p_jpeg_proc_mode() local
[all …]
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| D | jpeg-hw-exynos4.c | 21 unsigned int reg; in exynos4_jpeg_sw_reset() local
23 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
24 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
28 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
33 unsigned int reg; in exynos4_jpeg_set_enc_dec_mode() local
35 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
38 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
42 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode()
51 unsigned int reg; in __exynos4_jpeg_set_img_fmt() local
63 reg = readl(base + EXYNOS4_IMG_FMT_REG) & in __exynos4_jpeg_set_img_fmt()
[all …]
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| D | jpeg-hw-exynos3250.c | 23 u32 reg = 1; in exynos3250_jpeg_reset() local
28 while (reg != 0 && --count > 0) { in exynos3250_jpeg_reset()
31 reg = readl(regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset()
34 reg = 0; in exynos3250_jpeg_reset()
37 while (reg != 1 && --count > 0) { in exynos3250_jpeg_reset()
41 reg = readl(regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset()
65 u32 reg; in exynos3250_jpeg_clk_set() local
67 reg = readl(base + EXYNOS3250_JPGCMOD) & ~EXYNOS3250_HALF_EN_MASK; in exynos3250_jpeg_clk_set()
69 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_clk_set()
74 u32 reg; in exynos3250_jpeg_input_raw_fmt() local
[all …]
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| /drivers/staging/media/s5p-cec/ |
| D | exynos_hdmi_cecctrl.c | 29 unsigned int reg; in s5p_cec_set_divider() local
33 if (regmap_read(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, ®)) { in s5p_cec_set_divider()
38 reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16); in s5p_cec_set_divider()
40 if (regmap_write(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, reg)) { in s5p_cec_set_divider()
47 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_3); in s5p_cec_set_divider()
48 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_2); in s5p_cec_set_divider()
49 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_1); in s5p_cec_set_divider()
50 writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0); in s5p_cec_set_divider()
55 u8 reg; in s5p_cec_enable_rx() local
57 reg = readb(cec->reg + S5P_CEC_RX_CTRL); in s5p_cec_enable_rx()
[all …]
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| /drivers/video/fbdev/riva/ |
| D | nvreg.h | 44 #define DEVICE_ACCESS(device,reg) \ argument
45 nvCONTROL[(NV_##device##_##reg)/4]
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
48 #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) argument
49 #define DEVICE_PRINT(device,reg) \ argument
50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
57 #define PDAC_Read(reg) DEVICE_READ(PDAC,reg) argument
58 #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) argument
63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) argument
[all …]
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| /drivers/net/ethernet/microchip/ |
| D | encx24j600-regmap.c | 66 static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val, in regmap_encx24j600_sfr_read() argument
70 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_read()
71 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_read()
77 if (reg < 0x80) { in regmap_encx24j600_sfr_read()
87 switch (reg) { in regmap_encx24j600_sfr_read()
110 tx_buf[i++] = reg; in regmap_encx24j600_sfr_read()
118 u8 reg, u8 *val, size_t len, in regmap_encx24j600_sfr_update() argument
121 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_update()
122 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_update()
126 { .tx_buf = ®, .len = sizeof(reg), }, in regmap_encx24j600_sfr_update()
[all …]
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| /drivers/net/wireless/ralink/rt2x00/ |
| D | rt2400pci.c | 59 u32 reg; in rt2400pci_bbp_write() local
67 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_write()
68 reg = 0; in rt2400pci_bbp_write()
69 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2400pci_bbp_write()
70 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2400pci_bbp_write()
71 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2400pci_bbp_write()
72 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2400pci_bbp_write()
74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_write()
83 u32 reg; in rt2400pci_bbp_read() local
95 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_read()
[all …]
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| D | rt2500pci.c | 59 u32 reg; in rt2500pci_bbp_write() local
67 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2500pci_bbp_write()
68 reg = 0; in rt2500pci_bbp_write()
69 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2500pci_bbp_write()
70 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2500pci_bbp_write()
71 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2500pci_bbp_write()
72 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2500pci_bbp_write()
74 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2500pci_bbp_write()
83 u32 reg; in rt2500pci_bbp_read() local
95 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2500pci_bbp_read()
[all …]
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| D | rt61pci.c | 68 u32 reg; in rt61pci_bbp_write() local
76 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_write()
77 reg = 0; in rt61pci_bbp_write()
78 rt2x00_set_field32(®, PHY_CSR3_VALUE, value); in rt61pci_bbp_write()
79 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); in rt61pci_bbp_write()
80 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); in rt61pci_bbp_write()
81 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); in rt61pci_bbp_write()
83 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_write()
92 u32 reg; in rt61pci_bbp_read() local
104 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_read()
[all …]
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| D | rt2500usb.c | 62 __le16 reg; in rt2500usb_register_read() local
65 ®, sizeof(reg)); in rt2500usb_register_read()
66 *value = le16_to_cpu(reg); in rt2500usb_register_read()
73 __le16 reg; in rt2500usb_register_read_lock() local
76 ®, sizeof(reg), REGISTER_TIMEOUT); in rt2500usb_register_read_lock()
77 *value = le16_to_cpu(reg); in rt2500usb_register_read_lock()
93 __le16 reg = cpu_to_le16(value); in rt2500usb_register_write() local
96 ®, sizeof(reg)); in rt2500usb_register_write()
103 __le16 reg = cpu_to_le16(value); in rt2500usb_register_write_lock() local
106 ®, sizeof(reg), REGISTER_TIMEOUT); in rt2500usb_register_write_lock()
[all …]
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| D | rt73usb.c | 66 u32 reg; in rt73usb_bbp_write() local
74 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt73usb_bbp_write()
75 reg = 0; in rt73usb_bbp_write()
76 rt2x00_set_field32(®, PHY_CSR3_VALUE, value); in rt73usb_bbp_write()
77 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); in rt73usb_bbp_write()
78 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); in rt73usb_bbp_write()
79 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); in rt73usb_bbp_write()
81 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); in rt73usb_bbp_write()
90 u32 reg; in rt73usb_bbp_read() local
102 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt73usb_bbp_read()
[all …]
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| /drivers/net/ethernet/intel/ixgbe/ |
| D | ixgbe_dcb_82598.c | 46 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local
51 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; in ixgbe_dcb_config_rx_arbiter_82598()
52 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598()
54 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_rx_arbiter_82598()
56 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598()
58 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598()
60 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598()
62 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598()
69 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82598()
72 reg |= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598()
[all …]
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| D | ixgbe_dcb_82599.c | 51 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599() local
60 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82599()
61 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); in ixgbe_dcb_config_rx_arbiter_82599()
64 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599()
66 reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); in ixgbe_dcb_config_rx_arbiter_82599()
67 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); in ixgbe_dcb_config_rx_arbiter_82599()
73 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82599()
75 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; in ixgbe_dcb_config_rx_arbiter_82599()
78 reg |= IXGBE_RTRPT4C_LSP; in ixgbe_dcb_config_rx_arbiter_82599()
80 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); in ixgbe_dcb_config_rx_arbiter_82599()
[all …]
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| /drivers/acpi/pmic/ |
| D | intel_pmic_bxtwc.c | 38 .reg = 0x63,
43 .reg = 0x65,
48 .reg = 0x67,
53 .reg = 0x6d,
58 .reg = 0x6f,
63 .reg = 0x70,
68 .reg = 0x71,
73 .reg = 0x72,
78 .reg = 0x73,
83 .reg = 0x74,
[all …]
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| /drivers/media/pci/cx23885/ |
| D | cx23885-ioctl.c | 42 struct v4l2_dbg_register *reg) in cx23417_g_register() argument
49 if ((reg->reg & 0x3) != 0 || reg->reg >= 0x10000) in cx23417_g_register()
52 if (mc417_register_read(dev, (u16) reg->reg, &value)) in cx23417_g_register()
55 reg->size = 4; in cx23417_g_register()
56 reg->val = value; in cx23417_g_register()
61 struct v4l2_dbg_register *reg) in cx23885_g_register() argument
65 if (reg->match.addr > 1) in cx23885_g_register()
67 if (reg->match.addr) in cx23885_g_register()
68 return cx23417_g_register(dev, reg); in cx23885_g_register()
70 if ((reg->reg & 0x3) != 0 || reg->reg >= pci_resource_len(dev->pci, 0)) in cx23885_g_register()
[all …]
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| /drivers/net/ethernet/mellanox/mlxsw/ |
| D | reg.h | 75 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
101 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
121 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
128 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
134 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
140 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
174 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
181 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
189 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
199 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
[all …]
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| /drivers/clk/ |
| D | clk-highbank.c | 51 void __iomem *reg; member
59 u32 reg; in clk_pll_prepare() local
61 reg = readl(hbclk->reg); in clk_pll_prepare()
62 reg &= ~HB_PLL_RESET; in clk_pll_prepare()
63 writel(reg, hbclk->reg); in clk_pll_prepare()
65 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) in clk_pll_prepare()
67 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) in clk_pll_prepare()
76 u32 reg; in clk_pll_unprepare() local
78 reg = readl(hbclk->reg); in clk_pll_unprepare()
79 reg |= HB_PLL_RESET; in clk_pll_unprepare()
[all …]
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| /drivers/net/ethernet/sfc/ |
| D | io.h | 83 unsigned int reg) in _efx_writeq() argument
85 __raw_writeq((__force u64)value, efx->membase + reg); in _efx_writeq()
87 static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg) in _efx_readq() argument
89 return (__force __le64)__raw_readq(efx->membase + reg); in _efx_readq()
94 unsigned int reg) in _efx_writed() argument
96 __raw_writel((__force u32)value, efx->membase + reg); in _efx_writed()
98 static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg) in _efx_readd() argument
100 return (__force __le32)__raw_readl(efx->membase + reg); in _efx_readd()
105 unsigned int reg) in efx_writeo() argument
110 "writing register %x with " EFX_OWORD_FMT "\n", reg, in efx_writeo()
[all …]
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| /drivers/net/wireless/ath/ |
| D | regd.c | 26 static int __ath_regd_init(struct ath_regulatory *reg);
117 static bool dynamic_country_user_possible(struct ath_regulatory *reg) in dynamic_country_user_possible() argument
122 switch (reg->country_code) { in dynamic_country_user_possible()
189 static bool ath_reg_dyn_country_user_allow(struct ath_regulatory *reg) in ath_reg_dyn_country_user_allow() argument
193 if (!dynamic_country_user_possible(reg)) in ath_reg_dyn_country_user_allow()
205 static u16 ath_regd_get_eepromRD(struct ath_regulatory *reg) in ath_regd_get_eepromRD() argument
207 return reg->current_rd & ~WORLDWIDE_ROAMING_FLAG; in ath_regd_get_eepromRD()
210 bool ath_is_world_regd(struct ath_regulatory *reg) in ath_is_world_regd() argument
212 return is_wwr_sku(ath_regd_get_eepromRD(reg)); in ath_is_world_regd()
223 ieee80211_regdomain *ath_world_regdomain(struct ath_regulatory *reg) in ath_world_regdomain() argument
[all …]
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